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1. 发明申请

WO2018026527A1 PROVIDING AN INTERFACE FOR DEMOTION CONTROL INFORMATION IN A PROCESSOR 审中-公开
标题翻译：为处理器中的解决控制信息提供接口
公开(公告)号：WO2018026527A1
公开(公告)日：2018-02-08
申请号：PCT/US2017/042999
申请日：2017-07-20
申请人： INTEL CORPORATION
发明人： WEISSMANN, Eliezer , ROSENZWEIG, Nir , ROTEM, Efraim , BEN-RAPHAEL, Yoav , NAVEH, Alon
IPC分类号： G06F1/32 , G06F9/50
CPC分类号： G06F1/3287 , G06F1/3206 , G06F1/3296 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： In one embodiment, a processor includes: a plurality of cores; a power controller including a logic to autonomously demote a first request for at least one core of the plurality of cores to enter a first low power state, to cause the at least one core to enter a second low power state, the first low power state a deeper low power state than the second low power state; and an interface to receive an input from a system software, the input including at least one demotion control parameter, where the logic is to autonomously demote the first request based at least in part on the at least one demotion control parameter. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括：多个核心; 功率控制器，所述功率控制器包括逻辑，以自主降级对所述多个核心中的至少一个核心的第一请求以进入第一低功率状态，以使所述至少一个核心进入第二低功率状态，所述第一低功率状态比第二低功率状态更深的低功率状态; 以及用于接收来自系统软件的输入的接口，所述输入包括至少一个降级控制参数，其中所述逻辑至少部分地基于所述至少一个降级控制参数来自主降级所述第一请求。描述并要求保护其他实施例。

2. 发明申请

WO2017176358A1 SYSTEM POWER MANAGEMENT 审中-公开
标题翻译：系统电源管理
公开(公告)号：WO2017176358A1
公开(公告)日：2017-10-12
申请号：PCT/US2017/016732
申请日：2017-02-06
申请人： INTEL CORPORATION
发明人： ROTEM, Efraim , SCHIFF, Tod F , RAJWAN, Doron , JULL, Jeffrey M. , HERMERDING II, James G , ROSENZWEIG, Nir , TOLEDANO, Maytal , UAN-ZO-LI, Alexander B
IPC分类号： G06F1/32 , G05B23/02
摘要： One embodiment provides an apparatus. The apparatus includes power control logic and a critical comparator. The power control logic is to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin). The critical comparator is to compare a system power consumption value (Psys) and the critical threshold and to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.
摘要翻译：一个实施例提供了一种装置。该装置包括功率控制逻辑和关键比较器。功率控制逻辑至少部分地基于可用输入功率值（Pin）来确定临界阈值（TC）。关键比较器是比较系统功耗值（Psys）和临界阈值，并在系统功耗值大于或等于临界阈值时向处理器断言处理器关键节流信号。

3. 发明申请

WO2019040050A1 APPLICATION PRIORITY BASED POWER MANAGEMENT FOR A COMPUTER DEVICE 审中-公开
公开(公告)号：WO2019040050A1
公开(公告)日：2019-02-28
申请号：PCT/US2017/048059
申请日：2017-08-22
申请人： INTEL CORPORATION
发明人： ROTEM, Efraim , WEISSMANN, Eliezer , RAJWAN, Doron , AIZIK, Yoni , NATANZON, Esfir , ROSENZWEIG, Nir , SHULMAN, Nadav , PLACKLE, Bart
IPC分类号： G06F1/32 , G06F9/50
摘要： Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.

4. 发明申请

WO2017218123A1 CURRENT CONTROL FOR A MULTICORE PROCESSOR 审中-公开
标题翻译：多核处理器的电流控制
公开(公告)号：WO2017218123A1
公开(公告)日：2017-12-21
申请号：PCT/US2017/032718
申请日：2017-05-15
申请人： INTEL CORPORATION
发明人： GENDLER, Alexander , ROTEM, Efraim , ROSENZWEIG, Nir , SISTLA, Krishnakanth V. , CHOUBAL, Ashish V. , VARMA, Ankush
IPC分类号： G06F1/32
摘要： Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.
摘要翻译：本文公开了与用于多核处理器的电流控制相关联的设备，方法和存储介质。在实施例中，多核处理器可以包括多个模拟电流比较器，每个模拟电流比较器用于测量多核处理器的相应一个核的电流利用率。多核处理器可以包括一个或多个处理器，设备和/或电路，以基于来自相应的模拟电流比较器的测量结果使这些核心单独调节。在一些实施例中，多核处理器的存储器装置可存储可执行以操作多个功率管理代理以分别基于核心的当前测量的多个历史来确定是否发送节流请求的指令。

5. 发明申请

WO2016105677A1 SYSTEM MAXIMUM CURRENT PROTECTION 审中-公开
标题翻译：系统最大电流保护
公开(公告)号：WO2016105677A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/059762
申请日：2015-11-09
申请人： INTEL CORPORATION
发明人： ROTEM, Efraim , ROSENZWEIG, Nir , RAJWAN, Doron , SHULMAN, Nadav , LEIBOVICH, Gal , ZIV, Tomer , GABAI, Amit , RODRIGUEZ, Jorge P. , CARLSON, Jeffrey A.
IPC分类号： G06F1/28 , G06F1/26
CPC分类号： G06F1/324 , G05F1/10 , G06F1/28 , G06F1/3206 , H03L7/08 , Y02D10/126
摘要： A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
摘要翻译：一种用于提供主动电流保护的方法和装置。在一个实施例中，该方法包括：在转换到集成电路（IC）的新状态之前，通过针对多个域中的每个域计算预期电流来计算IC中多个域的预期功率之和在新状态的单个域频率上，将预期电流与其相关联的电压乘以用于新状态的多个域中的每一个; 将总和与功率限制进行比较; 并且如果所述和大于所述功率极限，则减少与所述多个域中的至少一个域相关联的各个域频率，以将所述IC的总瞬时功率维持在所述功率极限以下。

6. 发明申请

WO2020242991A1 DEVICE, METHOD AND SYSTEM FOR TRANSPARENTLY CHANGING A FREQUENCY OF AN INTERCONNECT FABRIC 审中-公开
公开(公告)号：WO2020242991A1
公开(公告)日：2020-12-03
申请号：PCT/US2020/034346
申请日：2020-05-22
申请人： INTEL CORPORATION
发明人： RANEL, Chen , LAKE, Christopher J. , DOSHI, Hem , MELAMED, Ido , DEGALAHAL, Vijay , SABIN, Yevgeni , PATEL, Reena , BEN-RAPHAEL, Yoav , ANGEL, Nimrod , ROTEM, Efraim , CONRAD, Shaun , ZIV, Tomer , ROSENZWEIG, Nir , NATANZON, Esfir , AIZIK, Yoni , GIHON, Arik , ABITAN, Natanel
IPC分类号： G06F1/3237 , G06F1/06
摘要： Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

7. 发明申请

WO2014143674A1 CONTROLLING POWER SUPPLY UNIT POWER CONSUMPTION DURING IDLE STATE 审中-公开
标题翻译：在空闲状态期间控制电源单元功耗
公开(公告)号：WO2014143674A1
公开(公告)日：2014-09-18
申请号：PCT/US2014/027730
申请日：2014-03-14
申请人： INTEL CORPORATION , ROTEM, Efraim , GOULD, Benjamin J. , HERMERDING II, James G. , RODRIGUEZ, Jorge P. , NAVEH, Alon , ROSENZWEIG, Nir , DEGALAHAL, Vijay S R
发明人： ROTEM, Efraim , GOULD, Benjamin J. , HERMERDING II, James G. , RODRIGUEZ, Jorge P. , NAVEH, Alon , ROSENZWEIG, Nir , DEGALAHAL, Vijay S R
IPC分类号： G06F1/32
CPC分类号： G06F1/325 , G06F1/3206 , Y02D50/20
摘要： Methods and apparatus relating to controlling power consumption by a Power Supply Unit (PSU) during idle state are described. In one embodiment, a power supply unit enters a lower power consumption state (e.g., S9) based on power state information, corresponding to one or more components of the platform, and comparison of a first value (corresponding to a frequency/frequentness of entry into the lower power consumption state) to a first threshold value. Other embodiments are also disclosed and claimed.
摘要翻译：描述了在空闲状态期间由电源单元（PSU）控制功率消耗的方法和装置。在一个实施例中，电源单元基于对应于平台的一个或多个组件的功率状态信息进入较低功耗状态（例如，S9），并且比较第一值（对应于入口的频率/频率进入较低功耗状态）达到第一阈值。还公开并要求保护其他实施例。

8. 发明申请

WO2014105140A1 TOTAL PLATFORM POWER CONTROL 审中-公开
标题翻译：总平台功率控制
公开(公告)号：WO2014105140A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/046541
申请日：2013-06-19
申请人： INTEL CORPORATION , ROTEM, Efraim , HERMERDING II, James G. , MA, Ruoying , RODRIGUEZ, Jorge P. , ROSENZWEIG, Nir
发明人： ROTEM, Efraim , HERMERDING II, James G. , MA, Ruoying , RODRIGUEZ, Jorge P. , ROSENZWEIG, Nir
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/206 , G06F1/324 , G06F1/325 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： Methods and apparatus relating to total platform power control are described. In one embodiment, power consumption by one or more processor cores of a processor and one or more components coupled to the processor are modified based on a total platform power consumption value. The platform, in turn, includes the processor and the one or more components. Other embodiments are also disclosed and claimed.
摘要翻译：描述了与平台总功率控制有关的方法和设备。在一个实施例中，基于总平台功耗值修改处理器的一个或多个处理器核心和耦合到处理器的一个或多个组件的功率消耗。该平台又包括处理器和一个或多个组件。还公开并要求保护其他实施例。

9. 发明申请

WO2019005392A1 SYSTEM, APPARATUS AND METHOD FOR LOOSE LOCK-STEP REDUNDANCY POWER MANAGEMENT 审中-公开
公开(公告)号：WO2019005392A1
公开(公告)日：2019-01-03
申请号：PCT/US2018/035042
申请日：2018-05-30
申请人： INTEL CORPORATION
发明人： ROTEM, Efraim , WEISSMANN, Eliezer , RAJWAN, Doron , ROSENZWEIG, Nir , AIZIK, Yoni
IPC分类号： G06F1/32 , G06F11/16
摘要： In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

10. 发明申请

WO2016191032A1 CONTROLLING PERFORMANCE STATES OF PROCESSING ENGINES OF A PROCESSOR 审中-公开
标题翻译：控制处理器处理发动机的性能状态
公开(公告)号：WO2016191032A1
公开(公告)日：2016-12-01
申请号：PCT/US2016/029923
申请日：2016-04-29
申请人： INTEL CORPORATION
发明人： WEISSMANN, Eliezer , ROTEM, Efraim , ABU SALAH, Hisham , AIZIK, Yoni , RAJWAN, Doron , ROSENZWEIG, Nir , LEIBOVICH, Gal , SABIN, Yevgeni , LEVY, Shay
IPC分类号： G06F1/32 , G06F9/28
CPC分类号： G06F1/3287 , G06F1/324 , G06F1/3243 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/152 , Y02D10/171 , Y02D10/172
摘要： In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括：多个处理引擎，包括独立执行指令的第一处理引擎和第二处理引擎; 以及功率控制器，其包括用于控制所述处理引擎中的至少一个的性能状态的性能状态控制逻辑，以及用于在第一窗口中确定所述主动处理引擎的平均数量的第一逻辑，所述处理器的估计活动级别并且至少部分地基于所估计的活动级别和所述第一窗口的比较来调整所述性能状态控制逻辑将执行性能状态确定和至少一个活动级别阈值的窗口长度中的至少一个平均主动处理引擎数。描述和要求保护其他实施例。

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