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1. 发明申请

WO2005109218A1 MEMORY CONTROLLER WITH COMMAND LOOK-AHEAD 审中-公开
标题翻译：内存控制器与命令前瞻
公开(公告)号：WO2005109218A1
公开(公告)日：2005-11-17
申请号：PCT/US2005/012089
申请日：2005-04-08
申请人： INTEL CORPORATION , NATARAJAN, Rohit , BERNSTEIN, Debra , WOLRICH, Gilbert , LIN, Chang-Ming
发明人： NATARAJAN, Rohit , BERNSTEIN, Debra , WOLRICH, Gilbert , LIN, Chang-Ming
IPC分类号： G06F13/16
CPC分类号： G06F13/161
摘要： In general, in one aspect, the disclosure describes accessing multiple memory access commands from a one of multiple memory access command queues associated with, respective, banks of a Random Access Memory (RAM) and selecting one of the commands based, at least in part, on the memory access operations identified by the commands and the memory access operation of a previously selected memory access command.
摘要翻译：通常，在一个方面，本公开描述了从与随机存取存储器（RAM）的相应的存储体组相关联的多个存储器访问命令队列之一访问多个存储器访问命令，并且至少部分地基于所述命令中的一个来选择一个命令关于由命令识别的存储器访问操作和先前选择的存储器访问命令的存储器访问操作。

2. 发明申请

WO2001016715A1 BRANCH INSTRUCTIONS IN A MULTITHREADED PARALLEL PROCESSING SYSTEM 审中-公开
标题翻译：分支指令在多个并行的并行处理系统中
公开(公告)号：WO2001016715A1
公开(公告)日：2001-03-08
申请号：PCT/US2000/023983
申请日：2000-08-31
申请人： INTEL CORPORATION , WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
发明人： WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
IPC分类号： G06F9/32
CPC分类号： G06F9/30018 , G06F9/3004 , G06F9/30058 , G06F9/30087 , G06F9/30145 , G06F9/30167 , G06F9/321 , G06F9/3834 , G06F9/3842 , G06F9/3851
摘要： A processor such as a parallel hardware-based multithreaded processor (12) is described. The processor can execute a computer instruction that is a branch instruction that causes an execution stream to branch to an instruction at an address specified in the instruction if a state of a specified state name of the processor is a specified value.
摘要翻译：描述诸如并行硬件的多线程处理器（12）之类的处理器。如果处理器的指定状态名称的状态是指定值，则处理器可以执行作为分支指令的计算机指令，该分支指令使执行流分支到指令中指定的地址处的指令。

3. 发明申请

WO2006069126A2 METHOD AND APPARATUS TO SUPPORT MULTIPLE MEMORY BANKS WITH A MEMORY BLOCK 审中-公开
标题翻译：用存储器块支持多个存储器银行的方法和设备
公开(公告)号：WO2006069126A2
公开(公告)日：2006-06-29
申请号：PCT/US2005/046297
申请日：2005-12-20
申请人： INTEL CORPORATION , JAIN, Sanjeev , WOLRICH, Gilbert , ROSENBLUTH, Mark , BERNSTEIN, Debra
发明人： JAIN, Sanjeev , WOLRICH, Gilbert , ROSENBLUTH, Mark , BERNSTEIN, Debra
IPC分类号： G06F13/16
CPC分类号： G06F13/1673
摘要： A memory controller system includes a memory command storage module to store commands for a plurality of memory banks. The system includes a plurality of control mechanisms, each of which includes first and second pointers, to provide, in combination with a next field in each module location, a link list of commands for a given one of the plurality of memory banks.
摘要翻译：存储器控制器系统包括用于存储用于多个存储体的命令的存储器命令存储模块。该系统包括多个控制机构，每个控制机构包括第一和第二指针，以与每个模块位置中的下一个字段结合提供用于多个存储体中给定的一个存储体的命令的链接列表。 p>

4. 发明申请

WO2001018646A1 BRANCH INSTRUCTION FOR MULTITHREADED PROCESSOR 审中-公开
标题翻译：多用途加工商分支指导
公开(公告)号：WO2001018646A1
公开(公告)日：2001-03-15
申请号：PCT/US2000/023992
申请日：2000-08-31
申请人： INTEL CORPORATION , WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
发明人： WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
IPC分类号： G06F9/38
CPC分类号： G06F9/30018 , G06F9/3004 , G06F9/30058 , G06F9/30087 , G06F9/30145 , G06F9/30167 , G06F9/321 , G06F9/3834 , G06F9/3842 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor (12) is described. The processor (12) includes a general purpose processor that coordinates system functions and a plurality of microengines (22a-22f) that support multiple hardware threads or contexts. The processor (12) also includes a memory control system (16) that has a first memory controller (26a) that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller (26b) that optimizes memory references based upon whether the memory references are read references or write references. Instructions for switching and branching based on executing contexts are also disclosed.
摘要翻译：描述了一种基于并行硬件的多线程处理器（12）。处理器（12）包括协调系统功能的通用处理器和支持多个硬件线程或上下文的多个微引擎（22a-22f）。处理器（12）还包括存储器控制系统（16），该存储器控制系统（16）具有第一存储器控制器（26a），该第一存储器控制器基于存储器参考是指向偶数存储器还是存储器的奇数存储器，并且第二存储器控制器（26b），其基于存储器引用是读取引用还是写入引用来优化存储器引用。还公开了基于执行上下文的切换和分支的指令。

5. 发明申请

WO2001016714A1 FAST WRITE INSTRUCTION FOR MICRO ENGINE USED IN MULTITHREADED PARALLEL PROCESSOR ARCHITECTURE 审中-公开
标题翻译：用于多路并行处理器架构的微型发动机的快速写入指令
公开(公告)号：WO2001016714A1
公开(公告)日：2001-03-08
申请号：PCT/US2000/024000
申请日：2000-08-31
申请人： INTEL CORPORATION , WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
发明人： WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
IPC分类号： G06F9/312
CPC分类号： G06F9/30018 , G06F9/3004 , G06F9/30058 , G06F9/30087 , G06F9/30145 , G06F9/30167 , G06F9/321 , G06F9/3834 , G06F9/3842 , G06F9/3851
摘要： A method of operating a processor (12) including receiving data in a processing thread having a processing thread number and shifting the data into a register corresponding to the processing thread number.
摘要翻译：一种操作处理器（12）的方法，包括在具有处理线程号的处理线程中接收数据，并将数据移位到与处理线程号相对应的寄存器中。

6. 发明申请

WO2001016758A3 DOUBLE SHIFT INSTRUCTION FOR MICRO ENGINE USED IN MULTITHREADED PARALLEL PROCESSOR ARCHITECTURE 审中-公开
公开(公告)号：WO2001016758A3
公开(公告)日：2001-03-08
申请号：PCT/US2000/023982
申请日：2000-08-31
申请人： INTEL CORPORATION , WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
发明人： WOLRICH, Gilbert , ADILETTA, Matthew, J. , WHEELER, William , BERNSTEIN, Debra , HOOPER, Donald
IPC分类号： G06F9/315
摘要： A method of operating a processor comprises concatenating a first word and a second word to produce an intermediate result. An ALU (76a) shifts the intermediate result by a specified shift amount and stores, in a register (76b), the shifted intermediate result in a third word.

7. 发明申请

WO2010077904A3 FILTER FOR NETWORK INTRUSION AND VIRUS DETECTION 审中-公开
公开(公告)号：WO2010077904A3
公开(公告)日：2010-07-08
申请号：PCT/US2009/068168
申请日：2009-12-16
申请人： INTEL CORPORATION , GOPAL, Vinodh , CLARK, Christopher, F. , WOLRICH, Gilbert , FEGHALI, Wajdi
发明人： GOPAL, Vinodh , CLARK, Christopher, F. , WOLRICH, Gilbert , FEGHALI, Wajdi
IPC分类号： H04L12/26 , G06F21/20
摘要： Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.

8. 发明申请

WO2009012050A3 DETERMINING A MESSAGE RESIDUE 审中-公开
公开(公告)号：WO2009012050A3
公开(公告)日：2009-01-22
申请号：PCT/US2008/068801
申请日：2008-06-30
申请人： INTEL CORPORATION , GUERON, Shay , GOPAL, Vinodh , FEGHALI, Wajdi, K. , WOLRICH, Gilbert
发明人： GUERON, Shay , GOPAL, Vinodh , FEGHALI, Wajdi, K. , WOLRICH, Gilbert
IPC分类号： G06F7/52
摘要： A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments of the message. The technique also includes determining a modular remainder with respect to the polynomial for the message based on the set of modular remainders and a set of constants determined prior to accessing the message. The modular remainder with respect to the polynomial for the message is stored in a memory.

9. 发明申请

WO2008027734A1 APPARATUS AND METHOD FOR GENERATING A GALOIS-FIELD SYNDROME 审中-公开
标题翻译：用于产生GALOIS-FIELD SYNDROME的装置和方法
公开(公告)号：WO2008027734A1
公开(公告)日：2008-03-06
申请号：PCT/US2007/076147
申请日：2007-08-16
申请人： INTEL CORPORATION , GOPAL, Vinodh , WOLRICH, Gilbert , CUTTER, Daniel , FEGHALI, Wajdi , OTTAVI, Robert, P.
发明人： GOPAL, Vinodh , WOLRICH, Gilbert , CUTTER, Daniel , FEGHALI, Wajdi , OTTAVI, Robert, P.
IPC分类号： G06F3/06 , G06F12/16
CPC分类号： G06F11/1076 , G06F2211/1054 , G06F2211/1057
摘要： The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于产生伽罗瓦域综合征的装置和方法。一个示例性方法可以包括将第一数据字节从第一存储设备加载到第一寄存器，并将第二数据字节从第二存储设备加载到第二寄存器; 将第一数据字节的最高有效位（MSB）和伽罗瓦域多项式进行比较以产生第一中间输出; 用第一数据字节的最低有效位（LSB）对第一中间输出的每个位进行异或，以产生第二中间输出; 将第二中间输出与第一数据字节的每个位进行多路复用以产生第三中间输出; 将第三中间输出的每个位与第二数据字节的每个位进行异或，以在第四中间输出处产生; 以及至少部分地基于第四中间输出产生RAID Q综合征。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

10. 发明申请

WO2006039183A3 EXPANSION OF COMPUTE ENGINE CODE SPACE BY SHARING ADJACENT CONTROL STORES USING INTERLEAVED PROGRAM ADDRESSES 审中-公开
公开(公告)号：WO2006039183A3
公开(公告)日：2006-04-13
申请号：PCT/US2005/034010
申请日：2005-09-21
申请人： INTEL CORPORATION , WOLRICH, Gilbert , ROSENBLUTH, Mark , ADILETTA, Matthew , WILKINSON, Hugh , NIELL, Jose , NARAYANAN, Rajagopal , JAIN, Sanjeev
发明人： WOLRICH, Gilbert , ROSENBLUTH, Mark , ADILETTA, Matthew , WILKINSON, Hugh , NIELL, Jose , NARAYANAN, Rajagopal , JAIN, Sanjeev
IPC分类号： G06F9/32
摘要： Method and apparatus to support expansion of compute engine code space by sharing adjacent control stores using interleaved addressing schemes. Instructions corresponding to an original instruction thread are partitioned into multiple interleaved sequences that are stored in respective control stores. During thread execution, instructions are retrieved from the control stores in a repeated order based on the interleaving scheme. For example, in one embodiment two compute engines share two control stores. Thus, instructions for a given thread are sequentially loaded from the control stores in an alternating manner. In another embodiment, four control stores are shared by four compute engines. In this case, the instructions in a thread are interleave using four stores, and each store is accessed every fourth instruction in the code sequence. Schemes are also provided for handling branching operations to maintain synchronized access to the control stores.

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