专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2008027734A1 APPARATUS AND METHOD FOR GENERATING A GALOIS-FIELD SYNDROME 审中-公开
标题翻译：用于产生GALOIS-FIELD SYNDROME的装置和方法
公开(公告)号：WO2008027734A1
公开(公告)日：2008-03-06
申请号：PCT/US2007/076147
申请日：2007-08-16
申请人： INTEL CORPORATION , GOPAL, Vinodh , WOLRICH, Gilbert , CUTTER, Daniel , FEGHALI, Wajdi , OTTAVI, Robert, P.
发明人： GOPAL, Vinodh , WOLRICH, Gilbert , CUTTER, Daniel , FEGHALI, Wajdi , OTTAVI, Robert, P.
IPC分类号： G06F3/06 , G06F12/16
CPC分类号： G06F11/1076 , G06F2211/1054 , G06F2211/1057
摘要： The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于产生伽罗瓦域综合征的装置和方法。一个示例性方法可以包括将第一数据字节从第一存储设备加载到第一寄存器，并将第二数据字节从第二存储设备加载到第二寄存器; 将第一数据字节的最高有效位（MSB）和伽罗瓦域多项式进行比较以产生第一中间输出; 用第一数据字节的最低有效位（LSB）对第一中间输出的每个位进行异或，以产生第二中间输出; 将第二中间输出与第一数据字节的每个位进行多路复用以产生第三中间输出; 将第三中间输出的每个位与第二数据字节的每个位进行异或，以在第四中间输出处产生; 以及至少部分地基于第四中间输出产生RAID Q综合征。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

2. 发明申请

WO2007078923A2 CRYPTOGRAPHY PROCESSING UNITS AND MULTIPLIER 审中-公开
标题翻译：图像处理单元和多路复用器
公开(公告)号：WO2007078923A2
公开(公告)日：2007-07-12
申请号：PCT/US2006/048293
申请日：2006-12-18
申请人： INTEL CORPORATION , HASENPLAUGH, William, C. , CUTTER, Daniel, F. , FEGHALI, Wajdi, K. , WOLRICH, Gilbert, M. , GAUBATZ, Gunnar , GOPAL, Vinodh
发明人： HASENPLAUGH, William, C. , CUTTER, Daniel, F. , FEGHALI, Wajdi, K. , WOLRICH, Gilbert, M. , GAUBATZ, Gunnar , GOPAL, Vinodh
IPC分类号： G06F9/38
CPC分类号： G06F7/52 , G06F9/3001 , G06F9/3881 , G06F9/3885 , G06F21/72
摘要： In general, in one aspect, the disclosure describes a system including multiple programmable processing units, a dedicated hardware multiplier, and at least one bus connecting the multiple processing units and multiplier.
摘要翻译：通常，在一个方面，本公开描述了包括多个可编程处理单元，专用硬件乘法器和连接多个处理单元和乘法器的至少一个总线的系统。

3. 发明申请

WO2007078939A2 MULTIPLIER 审中-公开
标题翻译：乘数
公开(公告)号：WO2007078939A2
公开(公告)日：2007-07-12
申请号：PCT/US2006/048417
申请日：2006-12-18
申请人： INTEL CORPORATION , FEGHALI, Wajdi, K. , HASENPLAUGH, William, C. , WOLRICH, Gilbert, M. , CUTTER, Daniel, F. , GOPAL, Vinodh , GAUBATZ, Gunnar
发明人： FEGHALI, Wajdi, K. , HASENPLAUGH, William, C. , WOLRICH, Gilbert, M. , CUTTER, Daniel, F. , GOPAL, Vinodh , GAUBATZ, Gunnar
IPC分类号： G06F7/525
CPC分类号： G06F7/5275
摘要： In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
摘要翻译：一般来说，在一个方面，本发明描述了一种乘法器，其包括并行配置的一组多个乘法器，其中多个乘法器的集合具有对第一操作数的访问和第二操作数的乘法，第一操作数具有多个段，第二操作数具有多个段具有多个段的操作数。所述乘法器还包括逻辑以将所述第二操作数的单个段重复地提供给所述多个乘法器集合的每个乘法器，并且将所述第一操作数的多个相应段提供给所述多个乘法器组中的各个乘法器，直到所述第二操作数已被提供给第一个操作数的每个段。该逻辑至少部分地基于第一操作数内的相应段的位置来移动多个乘法器组中不同的乘法器的输出。乘法器还包括耦合到逻辑的累加器。

4. 发明申请

WO2013095629A1 APPARATUS AND METHOD FOR VECTOR INSTRUCTIONS FOR LARGE INTEGER ARITHMETIC 审中-公开
标题翻译：用于大规模整数算术的矢量指令的装置和方法
公开(公告)号：WO2013095629A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067165
申请日：2011-12-23
申请人： INTEL CORPORATION , WOLRICH, Gilbert M. , YAP, Kirk S. , GUILFORD, James D. , OZTURK, Erdinc , GOPAL, Vinodh , FEGHALI, Wajdi K. , GULLEY, Sean M. , DIXON, Martin G.
发明人： WOLRICH, Gilbert M. , YAP, Kirk S. , GUILFORD, James D. , OZTURK, Erdinc , GOPAL, Vinodh , FEGHALI, Wajdi K. , GULLEY, Sean M. , DIXON, Martin G.
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/3016 , G06F7/525 , G06F7/57 , G06F9/3001 , G06F9/30036 , G06F9/3893
摘要： An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.
摘要翻译：描述了一种装置，其包括具有指令执行流水线的半导体芯片，该指令执行流水线具有一个或多个具有相应逻辑电路的执行单元，以便：a）执行将第一输入操作数与第二输入操作数相乘并且呈现下一部分的第一指令其中，第一和第二输入操作数是第一和第二输入向量的相应元素; b）执行第二指令，其将第一输入操作数和第二输入操作数相乘并呈现结果的上部，其中第一和第二输入操作数是第一和第二输入向量的相应元素; 以及c）执行加法指令，其中加法指令的相加的进位项被记录在掩码寄存器中。

5. 发明申请

WO2017030600A1 INSTRUCTIONS AND LOGIC TO PROVIDE SIMD SM3 CRYPTOGRAPHIC HASHING FUNCTIONALITY 审中-公开
标题翻译：说明和逻辑提供SIMD SM3 CRYPTOGRAPHIC HASHING功能
公开(公告)号：WO2017030600A1
公开(公告)日：2017-02-23
申请号：PCT/US2015/065134
申请日：2015-12-10
申请人： INTEL CORPORATION , WOLRICH, Gilbert M. , GOPAL, Vinodh , GULLEY, Sean M. , YAP, Kirk S. , FEGHALI, Wajdi K.
发明人： WOLRICH, Gilbert M. , GOPAL, Vinodh , GULLEY, Sean M. , YAP, Kirk S. , FEGHALI, Wajdi K.
IPC分类号： H04L9/06 , H04L9/32 , G06F9/38 , G06F15/80
CPC分类号： G06F9/30145 , G06F9/30007 , G06F9/30036 , G06F21/72
摘要： Instructions and logic provide SIMD SM3 cryptographic hashing functionality. Some embodiments include a processor comprising: a decoder to decode instructions for a SIMD SM3 message expansion, specifying first and second source data operand sets, and an expansion extent. Processor execution units, responsive to the instruction, perform a number of SM3 message expansions, from the first and second source data operand sets, determined by the specified expansion extent and store the result into a SIMD destination register. Some embodiments also execute instructions for a SIMD SM3 hash round-slice portion of the hashing algorithm, from an intermediate hash value input, a source data set, and a round constant set. Processor execution units perform a set of SM3 hashing round iterations upon the source data set, applying the intermediate hash value input and the round constant set, and store a new hash value result in a SIMD destination register.
摘要翻译：说明和逻辑提供SIMD SM3加密散列功能。一些实施例包括处理器，包括：解码器，用于解码SIMD SM3消息扩展的指令，指定第一和第二源数据操作数集合以及扩展范围。响应于指令的处理器执行单元从由指定扩展范围确定的第一和第二源数据操作数集执行多个SM3消息扩展，并将结果存储到SIMD目的地寄存器中。一些实施例还从中间散列值输入，源数据集和圆常数集合执行散列算法的SIMD SM3散列圆切片部分的指令。处理器执行单元在源数据集上执行一组SM3散列循环迭代，应用中间散列值输入和循环常数集合，并将新的散列值结果存储在SIMD目的寄存器中。

6. 发明申请

WO2013095648A1 THREE INPUT OPERAND VECTOR ADD INSTRUCTION THAT DOES NOT RAISE ARITHMETIC FLAGS FOR CRYPTOGRAPHIC APPLICATIONS 审中-公开
标题翻译：三个输入操作向量添加指令，不提供用于CRYPTOAPHAPH应用的算术标记
公开(公告)号：WO2013095648A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067230
申请日：2011-12-23
申请人： INTEL CORPORATION , FEGHALI, Wajdi K. , GOPAL, Vinodh , GUILFORD, James D. , OZTURK, Erdinc , WOLRICH, Gilbert M. , YAP, Kirk S. , GULLEY, Sean M. , DIXON, Martin G.
发明人： FEGHALI, Wajdi K. , GOPAL, Vinodh , GUILFORD, James D. , OZTURK, Erdinc , WOLRICH, Gilbert M. , YAP, Kirk S. , GULLEY, Sean M. , DIXON, Martin G.
IPC分类号： G06F9/30 , G06F9/302 , G06F9/38
CPC分类号： G06F21/602 , G06F9/30007 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30181
摘要： A method is described that includes performing the following within an instruction execution pipeline implemented on a semiconductor chip: summing three input vector operands through execution of a single instruction; and, not raising any arithmetic flags even though a result of the summing creates more bits than circuitry designed to transport the summation is able to transport.
摘要翻译：描述了一种方法，其包括在半导体芯片上实现的指令执行流水线内执行以下操作：通过执行单个指令对三个输入向量操作数相加; 并且，即使求和的结果产生比设计用于传送求和的电路更多的位能够传输，也不会提高任何算术标记。

7. 发明申请

WO2013095615A1 BITSTREAM PROCESSING USING COALESCED BUFFERS AND DELAYED MATCHING AND ENHANCED MEMORY WRITES 审中-公开
标题翻译：使用加密缓存和延迟匹配和增强存储器写入的BITSTREAM处理
公开(公告)号：WO2013095615A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067092
申请日：2011-12-23
申请人： INTEL CORPORATION , GOPAL, Vinodh , GUILFORD, Jim, D. , FEGHALI, Wajdi, K. , KARAKOYUNLU, Deniz , OZTURK, Erdnic , DIXON, Martin , AKDEMIR, Kahraman, D. , WOLRICH, Gilbert, M.
发明人： GOPAL, Vinodh , GUILFORD, Jim, D. , FEGHALI, Wajdi, K. , KARAKOYUNLU, Deniz , OZTURK, Erdnic , DIXON, Martin , AKDEMIR, Kahraman, D. , WOLRICH, Gilbert, M.
IPC分类号： H03M7/30
CPC分类号： H04L65/607 , H03M7/30 , H03M7/3086 , H04L65/608 , H04L69/04 , H04L69/22 , H04W28/06
摘要： Methods and apparatus for processing bitstreams and byte streams. According to one aspect, bitstream data is compressed using coalesced string match tokens with delayed matching. A matcher is employed to perform search string match operations using a shortened maximum string length search criteria, resulting in generation of a token stream having data and literal data. A distance match operation is performed on sequentially adjacent tokens to determine if they contain the same distance data. If they do, the len values of the tokens are added through use of a coalesce buffer. Upon detection of a distance non-match, a final coalesced length of a matching string is calculated and output along with the prior matching distance as a coalesced token. Also disclosed is a scheme for writing variable-length tokens into a bitstream under which token data is input into a bit accumulator and written to memory (or cache to be subsequently written to memory) as each token is processed in a manner that eliminates branch mispredict operations associated with detecting whether the bit accumulator is full or close to full.
摘要翻译：用于处理比特流和字节流的方法和装置。根据一个方面，使用具有延迟匹配的合并字符串匹配令牌来压缩比特流数据。使用匹配器来执行搜索字符串匹配操作，使用缩短的最大字符串长度搜索条件，导致生成具有数据和文字数据的令牌流。对顺序相邻的令牌执行距离匹配操作，以确定它们是否包含相同的距离数据。如果这样做，令牌的len值通过使用合并缓冲区来添加。在检测到距离不匹配时，计算匹配串的最终合并长度，并将其与先前匹配距离一起作为合并令牌输出。还公开了一种用于将可变长度令牌写入比特流的方案，在该比特流中，令牌数据被输入到比特累加器中，并且以消除分支错误预测的方式将每个令牌进行处理，并将其写入存储器（或高速缓存以随后写入存储器）检测位累加器是满或接近满的操作。

8. 发明申请

WO2011084214A3 METHOD AND APPARATUS FOR PERFORMING A SHIFT AND EXCLUSIVE OR OPERATION IN A SINGLE INSTRUCTION 审中-公开
公开(公告)号：WO2011084214A3
公开(公告)日：2011-07-14
申请号：PCT/US2010/054754
申请日：2010-10-29
申请人： INTEL CORPORATION , GOPAL, Vinodh , GUILFORD, James D. , OZTURK, Erdinc , FEGHALI, Wajdi , WOLRICH, Gilbert M. , DIXON, Martin G.
发明人： GOPAL, Vinodh , GUILFORD, James D. , OZTURK, Erdinc , FEGHALI, Wajdi , WOLRICH, Gilbert M. , DIXON, Martin G.
IPC分类号： G06F9/305 , G06F13/14 , G06F13/16
摘要： Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

9. 发明申请

WO2010077904A3 FILTER FOR NETWORK INTRUSION AND VIRUS DETECTION 审中-公开
公开(公告)号：WO2010077904A3
公开(公告)日：2010-07-08
申请号：PCT/US2009/068168
申请日：2009-12-16
申请人： INTEL CORPORATION , GOPAL, Vinodh , CLARK, Christopher, F. , WOLRICH, Gilbert , FEGHALI, Wajdi
发明人： GOPAL, Vinodh , CLARK, Christopher, F. , WOLRICH, Gilbert , FEGHALI, Wajdi
IPC分类号： H04L12/26 , G06F21/20
摘要： Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.

10. 发明申请

WO2013095547A1 APPARATUS AND METHOD OF EXECUTION UNIT FOR CALCULATING MULTIPLE ROUNDS OF A SKEIN HASHING ALGORITHM 审中-公开
标题翻译：执行单元的设备和方法，用于计算多圈Skein散列算法
公开(公告)号：WO2013095547A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066988
申请日：2011-12-22
申请人： INTEL CORPORATION , WOLRICH, Gilbert M. , YAP, Kirk S. , GUILFORD, James D. , OZTURK, Erdinc , GOPAL, Vinodh , FEGHALI, Wajdi K. , GULLEY, Sean M. , DIXON, Martin G.
发明人： WOLRICH, Gilbert M. , YAP, Kirk S. , GUILFORD, James D. , OZTURK, Erdinc , GOPAL, Vinodh , FEGHALI, Wajdi K. , GULLEY, Sean M. , DIXON, Martin G.
IPC分类号： G06F1/00 , G06F9/305 , G06F9/44
CPC分类号： G06F9/30029 , G06F9/30007 , G06F9/30018 , G06F9/30036 , G06F9/3885 , G06F9/3895 , H04L9/0643
摘要： An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows. a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.
摘要翻译：描述了一种包括指令流水线内的执行单元的装置。执行单元具有多级电路，其包括a）和b）如下。 a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）接收第一四进制字的第一输入和接收第二四进制字的第二输入; ii）具有分别耦合到第一和第二输入的一对输入的加法器; iii）旋转器，具有耦合到第二输入的相应输入; iv）XOR门，具有耦合到加法器的输出的第一输入和耦合到旋转器的输出的第二输入。 b）置换逻辑电路，其具有耦合到相应加法器的输入和多个混合逻辑部分的异或门输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式