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1. 发明申请

WO2018014515A1 TECHNOLOGIES FOR ADAPTIVE PROCESSING OF MULTIPLE BUFFERS 审中-公开
标题翻译：多缓冲区自适应处理技术
公开(公告)号：WO2018014515A1
公开(公告)日：2018-01-25
申请号：PCT/CN2016/114023
申请日：2016-12-31
申请人： INTEL CORPORATION , LIU, Xiaodong , DAI, Qihua , LI, Weigang , GOPAL, Vinodh
发明人： LIU, Xiaodong , DAI, Qihua , LI, Weigang , GOPAL, Vinodh
IPC分类号： G06F9/30
摘要： Technologies for adaptive processing of multiple buffers is disclosed. A compute device may establish a buffer queue to which applications can submit buffers to be processed, such as by hashing the submitted buffers. The compute device monitors the buffer queue and determines an efficient way of processing the buffer queue based on the number of buffers present. The compute device may process the buffers serially with a single processor core of the compute device or may process the buffers in parallel with single-instruction, multiple data (SIMD) instructions. The compute device may determine which method to use based on a comparison of the throughput of serially processing the buffers as compared to parallel processing the buffers, which may depend on the number of buffers in the buffer queue.
摘要翻译：公开了用于自适应处理多个缓冲器的技术。计算设备可以建立缓冲队列，应用程序可以向其提交要处理的缓冲区，例如通过散列提交的缓冲区。计算设备监视缓冲队列并基于存在的缓冲数目确定处理缓冲队列的有效方式。计算设备可以用计算设备的单个处理器核心串行处理缓冲器，或者可以用单指令多数据（SIMD）指令并行处理缓冲器。计算设备可以基于比较串行处理缓冲器的吞吐量与并行处理缓冲器的比较来确定使用哪种方法，这可以取决于缓冲器队列中的缓冲器的数量。

2. 发明申请

WO2022133875A1 PROTOCOL STATE AWARE POWER MANAGEMENT 审中-公开
公开(公告)号：WO2022133875A1
公开(公告)日：2022-06-30
申请号：PCT/CN2020/138904
申请日：2020-12-24
申请人： INTEL CORPORATION , MA, Liang , YU, Ping , ZHANG, Fan , LI, Weigang , ZENG, Xin , YE, Xiaolong
发明人： MA, Liang , YU, Ping , ZHANG, Fan , LI, Weigang , ZENG, Xin , YE, Xiaolong
IPC分类号： H04L29/06 , H04W76/10 , H04W76/30
摘要： Various systems and methods for implementing protocol state aware power management are described herein. A network interface device for implementing protocol state aware power management includes circuitry to provide a direct memory access interface; medium access control (MAC) circuitry to interface with a network; and control circuitry to: classify packets received at the MAC circuitry as packets used to open network connections or packets used to close network connections; maintain statistics of packets used to open network connections and packets used to close network connections; calculate a power hint based on the statistics of packets used to open connections and packets used to close network connections; and write a receive descriptor to a host memory using the direct memory access interface, the receive descriptor including a power hint field with the power hint, the power hint used by a host processor to scale processor power based on the power hint.

3. 发明申请

WO2020000401A1 Transparent Encryption 审中-公开
公开(公告)号：WO2020000401A1
公开(公告)日：2020-01-02
申请号：PCT/CN2018/093764
申请日：2018-06-29
申请人： INTEL CORPORATION , LI, Weigang , WEI, Changzheng , BARRY, John , TAHHAN, Maryam , SVENNEBRING, Jonas Alexander , MCDONNELL, Niall D. , LECKEY, Alexander , FLEMING, Patrick , MACNAMARA, Christopher , BROWNE, John Joseph
发明人： LI, Weigang , WEI, Changzheng , BARRY, John , TAHHAN, Maryam , SVENNEBRING, Jonas Alexander , MCDONNELL, Niall D. , LECKEY, Alexander , FLEMING, Patrick , MACNAMARA, Christopher , BROWNE, John Joseph
IPC分类号： G06F3/06
摘要： There is disclosed a computing apparatus, including: a memory; a memory encryption controller to encrypt at least a region of the memory; and a network interface to communicatively couple the computing apparatus to a remote host; wherein the memory encryption controller is configured to send an encrypted packet decryptable via an encryption key directly from the memory to the remote host via the network interface, bypassing a network protocol stack.

4. 发明申请

WO2018176238A1 TECHNOLOGIES FOR HYBRID FIELD-PROGRAMMABLE GATE ARRAY-APPLICATION-SPECIFIC INTEGRATED CIRCUIT CODE ACCELERATION 审中-公开
公开(公告)号：WO2018176238A1
公开(公告)日：2018-10-04
申请号：PCT/CN2017/078472
申请日：2017-03-28
申请人： INTEL CORPORATION , SMITH, Ned, M. , WEI, Changzheng , SHEN, Songwu , YANG, Ziye , WANG, Junyuan , LI, Weigang , YU, Wenqian
发明人： SMITH, Ned, M. , WEI, Changzheng , SHEN, Songwu , YANG, Ziye , WANG, Junyuan , LI, Weigang , YU, Wenqian
IPC分类号： G06F9/50
CPC分类号： G06F9/5044 , G06F2209/509
摘要： Technologies for hybrid acceleration of code include a computing device (100) having a processor (120), a field-programmable gate array (FPGA) (130), and an application-specific integrated circuit (ASIC) (132). The computing device (100) offloads a service request, such as a cryptographic request or a packet processing request, to the FPGA (130). The FPGA (130) performs one or more algorithmic tasks of an algorithm to perform the service request. The FPGA (130) determines one or more primitive tasks associated with an algorithm task and encapsulates each primitive task in a buffer that is accessible by the ASIC (132). The ASIC (132) performs the primitive tasks in response to encapsulation in the buffer, and the FPGA (130) returns results of the algorithm. The primitive operations may include cryptographic primitives such as modular exponentiation, modular multiplicative inverse, and modular multiplication. The results may be returned to the processor (120) or a network interface controller of the computing device (100).

5. 发明申请

WO2022198619A1 APPARATUS AND METHOD TO IMPLEMENT SHARED VIRTUAL MEMORY IN A TRUSTED ZONE 审中-公开
公开(公告)号：WO2022198619A1
公开(公告)日：2022-09-29
申请号：PCT/CN2021/083178
申请日：2021-03-26
申请人： INTEL CORPORATION , GUO, Kaijie , WANG, Junyuan , LUKOSHKOV, Maksim , LI, Weigang , ZENG, Xin
发明人： GUO, Kaijie , WANG, Junyuan , LUKOSHKOV, Maksim , LI, Weigang , ZENG, Xin
IPC分类号： G06F12/00
摘要： An apparatus and method to implement shared virtual memory in a trust zone. For example, one embodiment of a processor comprises: a plurality of cores; a memory controller coupled to the plurality of cores to establish a first private memory region in a system memory using a first key associated with a first trust domain of a first guest; an input/output memory management unit (IOMMU) coupled to the memory controller, the IOMMU to receive a memory access request by an input/output (IO) device, the memory access request comprising a first address space identifier and a guest virtual address (GVA), the IOMMU to access an entry in a first translation table using at least the first address space identifier to determine that the memory access request is directed to the first private memory region which is not directly accessible to the IOMMU, the IOMMU to generate an address translation request associated with the memory access request, wherein based on the address translation request, a virtual machine monitor (VMM) running on one or more of the plurality of cores is to initiate a secure transaction sequence with trust domain manager to cause a secure entry into the first trust domain to translate the GVA to a physical address based on the address space identifier, the IOMMU to receive the physical address from the VMM and to use the physical address to perform the requested memory access on behalf of the IO device.

6. 发明申请

WO2020000391A1 VIRTUAL STORAGE SERVICES FOR CLIENT COMPUTING DEVICES 审中-公开
公开(公告)号：WO2020000391A1
公开(公告)日：2020-01-02
申请号：PCT/CN2018/093737
申请日：2018-06-29
申请人： INTEL CORPORATION , WEI, Changzheng , YANG, Ziye , WANG, Junyuan , LIANG, Cunming , HOU, Junhua , LI, Weigang , YU, Ping , YANG, Yi , LI, Baoqian , ZENG, Xin
发明人： WEI, Changzheng , YANG, Ziye , WANG, Junyuan , LIANG, Cunming , HOU, Junhua , LI, Weigang , YU, Ping , YANG, Yi , LI, Baoqian , ZENG, Xin
IPC分类号： H04L29/06
摘要： Embodiments include apparatuses, methods, and systems including one or more servers and one or more storage devices, coupled with each other, to provide virtual storage service to store a file and meta data of the file for a client computing device. The file and the meta data of the file may be encrypted by the client computing device before providing to the virtual storage service. The file may be encrypted with a secret key of the client computing device, and the meta data of the file may be encrypted with a shared session key between the client computing device and the virtual storage service. The encrypted file may be stored in the one or more storage devices, and the encrypted meta data of the file may be stored in one or more secured areas of the one or more servers. Other embodiments may also be described and claimed.

7. 发明申请

WO2018120017A1 TECHNIQUES FOR KEY EXCHANGE TO ESTABLISH SECURE CONNECTION IN NETWORK FUNCTION VIRTUALIZATION ENVIRONMENT 审中-公开
公开(公告)号：WO2018120017A1
公开(公告)日：2018-07-05
申请号：PCT/CN2016/113494
申请日：2016-12-30
申请人： INTEL CORPORATION , LI, Weigang , ZHOU, Danny, Yigang , WEI, Changzheng
发明人： LI, Weigang , ZHOU, Danny, Yigang , WEI, Changzheng
IPC分类号： H04L9/08
CPC分类号： H04L9/0866 , H04L9/0822 , H04L9/0897 , H04L2209/60
摘要： An apparatus (800) for a key exchange to establish a secure connection in a network function virtualization environment. The apparatus (800) exchanges an encrypted session key (410) between virtual network functions (VNF-A, VNF-B, VNF-C) executed by respective virtual machines (160-1 to 160-N) to establish the secure connection over a network connection, and uses a hardware security module (150) coupled with a processor (110) that supports at least one of the respective virtual machines (160-1 to 160-N). The hardware security module (150) facilitates encryption and decryption of the exchanged encrypted session key (410) via use of a virtual network function fingerprint (210, 220) for at least one of the virtual network functions(VNF-A, VNF-B, VNF-C).

8. 发明申请

WO2022133879A1 DEVICE, SYSTEM, AND METHOD FOR INSPECTING DIRECT MEMORY ACCESS REQUESTS 审中-公开
公开(公告)号：WO2022133879A1
公开(公告)日：2022-06-30
申请号：PCT/CN2020/138920
申请日：2020-12-24
申请人： INTEL CORPORATION , GUO, Kaijie , ZENG, Xin , SMITH, Ned , LI, Weigang , WANG, Junyuan , SHEN, Songwu , FAN, Zijuan , HUO, Yao , LUKOSHKOV, Maksim , COQUEREL, Laurent
发明人： GUO, Kaijie , ZENG, Xin , SMITH, Ned , LI, Weigang , WANG, Junyuan , SHEN, Songwu , FAN, Zijuan , HUO, Yao , LUKOSHKOV, Maksim , COQUEREL, Laurent
IPC分类号： G06F12/1009
摘要： Techniques and mechanisms for determining an operation to be performed with a direct memory access (DMA) request. An inspection unit (105) is coupled between an input-output memory management unit (IOMMU) (120) and an endpoint device (118). The inspection unit (105) stores a registry (330) comprising entries (332) which each correspond to a respective address, and a respective one or more resources of the endpoint device (118). A given entry (332) of the registry (330) is created based on a message from the IOMMU (120) which indicates the successful completion of an address translation to facilitate a DMA request. The endpoint device (118) performs a search, based on a DMA request, to determine if any registry (330) entry (332) indicates a combination of an address and an endpoint resource, where said combination matches a corresponding combination indicated by the DMA request. Communication of the DMA request to the IOMMU (120) is contingent on a result of the search.

9. 发明申请

WO2022133716A1 PROCESSOR CIRCUITRY TO EXECUTE AN INPUT-OUTPUT TRANSLATE VIRTUAL ADDRESS INSTRUCTION 审中-公开
公开(公告)号：WO2022133716A1
公开(公告)日：2022-06-30
申请号：PCT/CN2020/138270
申请日：2020-12-22
申请人： INTEL CORPORATION , GUO, Kaijie , LI, Weigang , WANG, Junyuan
发明人： GUO, Kaijie , LI, Weigang , WANG, Junyuan
IPC分类号： G06F12/10
摘要： Techniques and mechanisms for performing an address translation to facilitate a direct memory access. In an embodiment, a processor comprises circuitry to execute an instruction based on an instruction set, wherein the instruction indicates a first address of a first address space. Such execution results in an address translation that provides an input/output memory management unit (IOMMU) with a corresponding physical address of a memory region which is to be used in a direct memory access job. In another embodiment, the address translation is performed independent of a communication, received by IOMMU, which requests the performance of a particular DMA job using the second address.

10. 发明申请

WO2022198548A1 PASID GRANULARITY RESOURCE CONTROL FOR IOMMU 审中-公开
公开(公告)号：WO2022198548A1
公开(公告)日：2022-09-29
申请号：PCT/CN2021/082908
申请日：2021-03-25
申请人： INTEL CORPORATION , GUO, Kaijie , RAJ, Ashok , SMITH, Ned , LI, Weigang , WANG, Junyuan , ZENG, Xin , WILL, Brian , FAN, Zijuan , KOUNAVIS, Michael E. , XIE, Qianjun , WANG, Yuan , HUO, Yao
发明人： GUO, Kaijie , RAJ, Ashok , SMITH, Ned , LI, Weigang , WANG, Junyuan , ZENG, Xin , WILL, Brian , FAN, Zijuan , KOUNAVIS, Michael E. , XIE, Qianjun , WANG, Yuan , HUO, Yao
IPC分类号： G06F13/00
摘要： An embodiment of an integrated circuit may comprise memory to store respective resource control descriptors in correspondence with respective identifiers, and an input/output (IO) memory management unit (IOMMU) communicatively coupled to the memory, the IOMMU including circuitry to determine resource control information for an IO transaction based on a resource control descriptor stored in the memory that corresponds to an identifier associated with the IO transaction, and control utilization of one or more resources of the IOMMU based on the determined resource control information. Other embodiments are disclosed and claimed.

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