专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2014116496A1 METAL-INSULATOR-METAL CAPACITOR FORMATION TECHNIQUES 审中-公开
标题翻译：金属绝缘体 - 金属电容器形成技术
公开(公告)号：WO2014116496A1
公开(公告)日：2014-07-31
申请号：PCT/US2014/011856
申请日：2014-01-16
申请人： INTEL CORPORATION , KOBRINSKY, Mauro J. , BRISTOL, Robert L. , MAYBERRY, Michael C.
发明人： KOBRINSKY, Mauro J. , BRISTOL, Robert L. , MAYBERRY, Michael C.
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L28/60 , H01L21/0337 , H01L27/224 , H01L28/82
摘要： Techniques and structure are disclosed for providing a MIM capacitor having a generally corrugated profile. The corrugated topography is provisioned using sacrificial, self-organizing materials that effectively create a pattern in response to treatment (heat or other suitable stimulus), which is transferred to a dielectric material in which the MIM capacitor is formed. The self-organizing material may be, for example, a layer of directed self-assembly material that segregates into two alternating phases in response to heat or other stimulus, wherein one of the phases then can be selectively etched with respect to the other phase to provide the desired pattern. In another example case, the self-organizing material is a layer of material that coalesces into isolated islands when heated. As will be appreciated in light of this disclosure, the disclosed techniques can be used, for example, to increase capacitance per unit area, which can be scaled by etching deeper capacitor trenches/holes.
摘要翻译：公开了用于提供具有大体波形轮廓的MIM电容器的技术和结构。使用牺牲性自组织材料提供波纹形状，其有效地产生响应于被形成MIM电容器的介电材料的处理（热或其它合适的刺激）的图案。自组织材料可以是例如响应于热或其它刺激而分离成两个交替相的定向自组装材料层，其中相中的一个相可以相对于另一相被选择性地蚀刻到提供所需的图案。在另一个例子中，自组织材料是在加热时聚结成孤岛的材料层。根据本公开将会理解，所公开的技术可以用于例如增加每单位面积的电容，其可以通过蚀刻更深的电容器沟槽/孔来缩放。

2. 发明申请

WO2016175782A1 MICROELECTRONIC CONDUCTIVE ROUTES AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：微电子导电路线及其制造方法
公开(公告)号：WO2016175782A1
公开(公告)日：2016-11-03
申请号：PCT/US2015/028209
申请日：2015-04-29
申请人： INTEL CORPORATION , CHAWLA, Jasmeet S. , HOURANI, Rami , KOBRINSKY, Mauro J. , GSTREIN, Florian , CLENDENNING, Scott B. , ROBERTS, Jeanette M.
发明人： CHAWLA, Jasmeet S. , HOURANI, Rami , KOBRINSKY, Mauro J. , GSTREIN, Florian , CLENDENNING, Scott B. , ROBERTS, Jeanette M.
IPC分类号： H01L21/768
CPC分类号： H01L23/528 , H01L21/76802 , H01L21/76831 , H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L2221/1063
摘要： A conductive route structure may be formed comprising a conductive trace and a conductive via, wherein the conductive via directly contacts the conductive trace. In one embodiment, the conductive route structure may be formed by forming a dielectric material layer on the conductive trace. A via opening may be formed through the dielectric material layer to expose a portion of the conductive trace and a blocking layer may be from only on the exposed portion of the conductive trace. A barrier line may be formed on sidewalls of the via opening and the blocking layer may thereafter be removed. A conductive via may then be formed within the via opening, wherein the conductive via directly contacts the conductive trace.
摘要翻译：可以形成包括导电迹线和导电通孔的导电路径结构，其中导电通孔直接接触导电迹线。在一个实施例中，可以通过在导电迹线上形成介电材料层来形成导电路径结构。可以通过介电材料层形成通孔开口以暴露导电迹线的一部分，并且阻挡层可以仅来自导电迹线的暴露部分。可以在通孔开口的侧壁上形成阻挡线，然后可以去除阻挡层。然后可以在通孔开口内形成导电通孔，其中导电通孔直接接触导电迹线。

3. 发明申请

WO2017052562A1 METHODS OF FORMING BACKSIDE SELF-ALIGNED VIAS AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：形成背面自对准VIAS的方法及其形成的结构
公开(公告)号：WO2017052562A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052033
申请日：2015-09-24
申请人： INTEL CORPORATION , MORROW, Patrick , KOBRINSKY, Mauro J. , JUN, Kimin , SON, Il-Seok , FISCHER, Paul B.
发明人： MORROW, Patrick , KOBRINSKY, Mauro J. , JUN, Kimin , SON, Il-Seok , FISCHER, Paul B.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/41791 , H01L21/845 , H01L27/1211
摘要： Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.
摘要翻译：描述了由此形成的方法和结构，用于形成用于微电子器件的自对准接触结构。实施例包括在设置在器件层中的晶体管器件的源极/漏极区域中形成沟槽，其中器件层位于衬底上，在沟槽中形成填充材料，在填充材料上形成源极/漏极材料，在源极/漏极材料的第一侧上形成第一源极/漏极接触，然后在源极/漏极材料的第二侧上形成第二源极漏极接触。

4. 发明申请

WO2014120459A1 TECHNIQUES FOR ENHANCING FRACTURE RESISTANCE OF INTERCONNECTS 审中-公开
标题翻译：提高互连电阻的技术
公开(公告)号：WO2014120459A1
公开(公告)日：2014-08-07
申请号：PCT/US2014/011858
申请日：2014-01-16
申请人： INTEL CORPORATION , JEZEWSKI, Christopher J. , KOBRINSKY, Mauro J. , PANTUSO, Daniel , BHINGARDE, Siddharth B. , O'DAY, Michael P.
发明人： JEZEWSKI, Christopher J. , KOBRINSKY, Mauro J. , PANTUSO, Daniel , BHINGARDE, Siddharth B. , O'DAY, Michael P.
IPC分类号： H01L21/28
CPC分类号： H01L23/562 , H01L23/293 , H01L23/481 , H01L23/522 , H01L23/5221 , H01L23/5226 , H01L23/528 , H01L23/5329 , H01L23/535 , H01L23/5381 , H01L23/5386 , H01L2924/0002 , H01L2924/00
摘要： Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.
摘要翻译：公开了通过增加通孔密度来提高后端互连和其它这种互连结构的抗断裂性的技术和结构。可以例如在模具内的相邻电路层的填充/加工部分内提供通孔密度的增加。在一些情况下，上电路层的电隔离（浮置）填充线可以包括在对应于填充线交叉/相交的区域中的下电路层的浮动填充线上的通孔。在一些这样的情况下，上电路层的浮动填充线可以形成为包括这种通孔的双镶嵌结构。在一些实施例中，可以在上电路层的浮动填充线和下电路层的充分电隔离的互连线之间提供通孔。技术/结构可用于为模具提供机械完整性。

5. 发明申请

WO2012135483A2 OPTICAL WAVEGUIDE STRUCTURE 审中-公开
标题翻译：光波导结构
公开(公告)号：WO2012135483A2
公开(公告)日：2012-10-04
申请号：PCT/US2012/031187
申请日：2012-03-29
申请人： INTEL CORPORATION , KOBRINSKY, Mauro J. , BLOCK, Bruce A. , CHANG, Peter L.
发明人： KOBRINSKY, Mauro J. , BLOCK, Bruce A. , CHANG, Peter L.
IPC分类号： G02B6/122
CPC分类号： G02F1/035 , G02F1/025 , G02F1/065 , G02F1/225 , G02F2201/18
摘要： Embodiments of the invention describe a multi-segment optical waveguide that enables an optical modulator to be low-power and athermal by decreasing the device length needed for a given waveguide length. Embodiments of the invention describe an optical waveguide that is folded onto itself, and thus includes at least two sections. Thus, embodiments of the invention may decrease the device size of a modulator by at least around a factor of two if the device is folded twofold (device size may be further reduced if the modulator is folded threefold, fourfold, five-fold, etc.). Embodiments of the invention further enable the electrode length required to create the desired electro-optic effect for the multi- segment optical waveguide to be reduced. In embodiments of the invention, certain electrodes may be "shared" amongst the different segments of the waveguide, thereby reducing the power requirement and capacitance of a device having a waveguide of a given length.
摘要翻译：本发明的实施例描述了一种多段光波导，其通过减小给定波导长度所需的器件长度，使光调制器能够实现低功率和无热性。本发明的实施例描述了折叠到其自身上的光波导，因此包括至少两个部分。因此，如果器件被折叠两倍，则本发明的实施例可以将调制器的器件尺寸减小至少约二分之一（如果调制器被折叠三倍，四倍，五倍等等，则器件尺寸可以进一步降低））。本发明的实施例还使得能够减少为多段光波导产生期望的电光效应所需的电极长度。在本发明的实施例中，某些电极可以在波导的不同部分之间“共享”，由此降低具有给定长度的波导的器件的功率需求和电容。

6. 发明申请

WO2018182649A1 LAYERED OXYGEN BARRIER ELECTRODES FOR RESISTIVE RANDOM ACCESS MEMORY (RRAM) DEVICES AND THEIR METHODS OF FABRICATION 审中-公开
公开(公告)号：WO2018182649A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/025184
申请日：2017-03-30
申请人： INTEL CORPORATION , KARPOV, Elijah V. , JEZEWSKI, Christopher J. , KOBRINSKY, Mauro J.
发明人： KARPOV, Elijah V. , JEZEWSKI, Christopher J. , KOBRINSKY, Mauro J.
IPC分类号： H01L45/00
CPC分类号： H01L45/08 , H01L27/2436 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1675
摘要： A resistive random access memory (RRAM) device includes a bottom electrode disposed above a substrate, a top electrode disposed above the bottom electrode, an oxygen exchange layer disposed between the bottom electrode and the top electrode and a switching layer disposed between the bottom electrode and the top electrode. In an embodiment, the bottom or the top electrode includes at least two conductive layers, a first conductive layer and a second conductive layer disposed on the first conductive layer, where the first conductive layer has grain boundaries that are offset from grain boundaries of the second conductive layer.

7. 发明申请

WO2013133794A1 OPTICAL COUPLING TECHNIQUES AND CONFIGURATIONS BETWEEN DIES 审中-公开
标题翻译：光耦合技术及其配置
公开(公告)号：WO2013133794A1
公开(公告)日：2013-09-12
申请号：PCT/US2012/027793
申请日：2012-03-05
申请人： INTEL CORPORATION , KOBRINSKY, Mauro J. , TSENG, Jia-Hung , BLOCK, Bruce A.
发明人： KOBRINSKY, Mauro J. , TSENG, Jia-Hung , BLOCK, Bruce A.
IPC分类号： H01L31/12
CPC分类号： H01L31/16 , G02B6/12002 , G02B6/1228 , G02B6/125 , G02B6/42 , H01L33/58 , H01S5/026 , H01S5/0262
摘要： Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an opto-electronic assembly includes a first semiconductor die including a light source to generate light, and a first mode expander structure comprising a first optical material disposed on a surface of the first semiconductor die, the first optical material being optically transparent at a wavelength of the light, and a second semiconductor die including a second mode expander structure comprising a second optical material disposed on a surface of the second semiconductor die, the second material being optically transparent at the wavelength of the light, wherein the second optical material is evanescently coupled with the first optical material to receive the light from the first optical material. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供光学连接技术和配置。在一个实施例中，光电组件包括包括用于产生光的光源的第一半导体管芯和包括设置在第一半导体管芯的表面上的第一光学材料的第一模式扩展器结构，第一光学材料是光学透明的以及包括第二模式扩展器结构的第二半导体管芯，所述第二模式扩展器结构包括设置在所述第二半导体管芯的表面上的第二光学材料，所述第二材料在所述光的波长处是光学透明的，其中所述第二光学材料与第一光学材料瞬时耦合以接收来自第一光学材料的光。可以描述和/或要求保护其他实施例。

8. 发明申请

WO2013101184A1 OPTICAL I/O SYSTEM USING PLANAR LIGHT-WAVE INTEGRATED CIRCUIT 审中-公开
标题翻译：使用平面光波集成电路的光学I / O系统
公开(公告)号：WO2013101184A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068105
申请日：2011-12-30
申请人： INTEL CORPORATION , KOBRINSKY, Mauro J. , BRAUNISCH, Henning , LIFF, Shawna M. , CHANG, Peter L. , BLOCK, Bruce A. , SWAN, Johanna M.
发明人： KOBRINSKY, Mauro J. , BRAUNISCH, Henning , LIFF, Shawna M. , CHANG, Peter L. , BLOCK, Bruce A. , SWAN, Johanna M.
IPC分类号： G02B6/12 , G02B6/24
CPC分类号： G02B6/12004 , G02B6/12 , G02B6/30 , G02B6/4214 , G02B6/4257 , G02B6/428 , G02B2006/12061 , G02B2006/12121 , G02B2006/12123 , H01L21/563 , H01L23/49827 , H01L23/49838 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/167 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/81011 , H01L2224/81024 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/83048 , H01L2224/83102 , H01L2224/83986 , H01L2224/92125 , H01L2924/12042 , H01L2924/12043 , H01L2924/1431 , H01L2924/1432 , H01L2924/15311 , H01L2924/15312 , H04B10/25 , H04B10/40 , H04B10/801 , H01L2924/00014 , H01L2924/014
摘要： Photonic components are placed on the processor package to bring the optical signal close to the processor die. The processor package includes a substrate to which the processor die is coupled, and which allows the processor die to connect to a printed circuit board. The processor package also includes transceiver logic, electrical-optical conversion circuits, and an optical coupler. The electrical-optical conversion circuits can include laser(s), modulator(s), and photodetector(s) to transmit and receive and optical signal. The coupler interfaces to a fiber that extends off the processor package. Multiple fibers can be brought to the processor package allowing for a scalable high-speed, high-bandwidth interconnection to the processor.
摘要翻译：光子元件放置在处理器封装上，使光信号靠近处理器管芯。处理器封装包括处理器管芯耦合到其上的基板，并且允许处理器管芯连接到印刷电路板。处理器封装还包括收发器逻辑，电光转换电路和光耦合器。电光转换电路可以包括激光器，调制器和用于发射和接收光信号的光电检测器。耦合器连接到从处理器封装延伸的光纤。多个光纤可以被带到处理器封装，允许与处理器的可扩展的高速，高带宽互连。

9. 发明申请

WO2022119622A1 INTEGRATED CIRCUIT ASSEMBLIES WITH DIRECT CHIP ATTACH TO CIRCUIT BOARDS 审中-公开
公开(公告)号：WO2022119622A1
公开(公告)日：2022-06-09
申请号：PCT/US2021/051886
申请日：2021-09-24
申请人： INTEL CORPORATION
发明人： GOMES, Wilfred , SHARMA, Abhishek A. , INGERLY, Doug B. , GANESAN, Sanka , KOBRINSKY, Mauro J. , FISCHER, Kevin J.
IPC分类号： H01L23/538 , H01L23/00
摘要： Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

10. 发明申请

WO2018106267A1 INTEGRATED CIRCUIT DEVICE WITH BACK-SIDE INTERCONNECTION TO DEEP SOURCE / DRAIN SEMICONDUCTOR 审中-公开
公开(公告)号：WO2018106267A1
公开(公告)日：2018-06-14
申请号：PCT/US2016/068564
申请日：2016-12-23
申请人： INTEL CORPORATION
发明人： MORROW, Patrick , KOBRINSKY, Mauro J. , BOHR, Mark T. , GHANI, Tahir , MEHANDRU, Rishabh
IPC分类号： H01L29/772 , H01L29/78 , H01L29/417
摘要： Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式