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1. 发明申请

WO2021179281A1 OPTIMIZING LOW PRECISION INFERENCE MODELS FOR DEPLOYMENT OF DEEP NEURAL NETWORKS 审中-公开
公开(公告)号：WO2021179281A1
公开(公告)日：2021-09-16
申请号：PCT/CN2020/079161
申请日：2020-03-13
申请人： INTEL CORPORATION , GONG, Jiong , WU, Yong , SHEN, Haihao , LIN, Xiao Dong , ZHANG, Guoming , YUAN, Feng
发明人： GONG, Jiong , WU, Yong , SHEN, Haihao , LIN, Xiao Dong , ZHANG, Guoming , YUAN, Feng
IPC分类号： G06N3/04
摘要： Systems, apparatuses and methods may provide technology for optimizing an inference neural network model that performs asymmetric quantization by generating a quantized neural network, wherein model weights of the neural network are quantized as signed integer values, and wherein an input layer of the neural network is configured to quantize input values as unsigned integer values, generating a weights accumulation table based on the quantized model weights and a kernel size for the neural network, and generating an output restoration function for an output layer of the neural network based on the weights accumulation table and the kernel size. The technology may also perform per-input channel quantization. The technology may also perform mixed-precision auto-tuning.

2. 发明申请

WO2016095156A1 TRANSLATION CACHE CLOSURE AND PERSISTENT SNAPSHOT IN DYNAMIC CODE GENERATING SYSTEM SOFTWARE 审中-公开
标题翻译：动态代码生成系统软件中的翻译缓存关闭和备忘录
公开(公告)号：WO2016095156A1
公开(公告)日：2016-06-23
申请号：PCT/CN2014/094199
申请日：2014-12-18
申请人： INTEL CORPORATION , WU, Yong , LIN, Xiao Dong , YU, Jiajia , ZHONG, Xueliang
发明人： WU, Yong , LIN, Xiao Dong , YU, Jiajia , ZHONG, Xueliang
IPC分类号： G06F9/45
CPC分类号： G06F12/0815 , G06F9/4552 , G06F12/0808 , G06F12/0868
摘要： Systems and methods may provide translation cache closure and consistent data recovery in dynamic code generating system. An apparatus may group translation cache together and restore a translation cache snapshot as a whole. Chaining between translations may be maintained during saving and restoration.
摘要翻译：系统和方法可以提供动态代码生成系统中的翻译缓存关闭和一致的数据恢复。一种装置可以将翻译缓存组合在一起，并将整个翻译缓存快照恢复。在保存和恢复期间，可能会维持翻译之间的链接。

3. 发明申请

WO2016090554A1 SYSTEM AND METHOD FOR EXECUTION OF APPLICATION CODE COMPILED ACCORDING TO TWO INSTRUCTION SET ARCHITECTURES 审中-公开
标题翻译：用于执行根据两个指令集结构编译的应用代码的系统和方法
公开(公告)号：WO2016090554A1
公开(公告)日：2016-06-16
申请号：PCT/CN2014/093373
申请日：2014-12-09
申请人： INTEL CORPORATION , WU, Yong , LIN, Xiao Dong , JIN, Yihua , ZHONG, Xueliang , LI, Jianhui
发明人： WU, Yong , LIN, Xiao Dong , JIN, Yihua , ZHONG, Xueliang , LI, Jianhui
IPC分类号： G06F9/40
CPC分类号： G06F9/541 , G06F8/41 , G06F9/30145 , G06F9/4552 , G06F9/45533
摘要： Methods, apparatuses and storage medium associated with execution of application (118) code having multiple ISAs, are disclosed. In various embodiments, a runtime environment (104) may execute application (118) code having multiple instruction set architectures. The runtime environment (104) may be configured to execute first code (120) of the application (118) code according to a first instruction set architecture, while also configured to execute second code (122) of the application (118) code according to a second instruction set architecture that extends the first instruction set architecture. Using gates (124), the runtime environment (104) may be adapted to adapt an interaction from the first code (120) to the second instruction set architecture and/or adapt an interaction from the second code (122) to the first instruction set architecture and, subsequently, return to executing the application (118) code according to the first instruction set architecture or the second instruction set architecture, respectively. Other embodiments may be disclosed.
摘要翻译：公开了与执行具有多个ISA的应用程序（118）代码相关联的方法，装置和存储介质。在各种实施例中，运行时环境（104）可以执行具有多个指令集架构的应用（118）代码。运行时环境（104）可以被配置为根据第一指令集架构来执行应用程序（118）代码的第一代码（120），同时还被配置为根据应用程序（118）代码执行第二代码（122）代码扩展第一指令集架构的第二指令集体系结构。使用门（124），运行时环境（104）可以适于使来自第一代码（120）到第二指令集架构的交互和/或使从第二代码（122）到第一指令集的交互并且随后分别根据第一指令集架构或第二指令集架构返回执行应用程序（118）代码。可以公开其他实施例。

4. 发明申请

WO2021119907A1 TECHNOLOGY TO MININIMIZE NEGATIVE IMPACT OF CACHE CONFLICTS CAUSED BY INCOMPATIBLE LEADING DIMENSIONS IN MATRIX MULTIPLICATION AND CONVOLUTION KERNELS WITHOUT DIMENSION PADDING 审中-公开
公开(公告)号：WO2021119907A1
公开(公告)日：2021-06-24
申请号：PCT/CN2019/125599
申请日：2019-12-16
申请人： INTEL CORPORATION , WU, Yong , LIN, Xiaodong , CAO, Zhong , YUAN, Feng , LIU, Hongzhen
发明人： WU, Yong , LIN, Xiaodong , CAO, Zhong , YUAN, Feng , LIU, Hongzhen
IPC分类号： G06F17/16
摘要： Systems, apparatuses and methods may provide for technology that determines a ratio of floating point instructions to memory read instructions and controls a dimension size of a matrix kernel based at least in part on the ratio. In one example, the matrix kernel conducts an operation between a first matrix and a second matrix and the technology reuses elements of the first matrix for multiple vector lines of the second matrix.

5. 发明申请

WO2021087841A1 INTERLEAVED DATA CONVERSION TO CHANGE DATA FORMATS 审中-公开
公开(公告)号：WO2021087841A1
公开(公告)日：2021-05-14
申请号：PCT/CN2019/116172
申请日：2019-11-07
申请人： INTEL CORPORATION , WU, Yong , HAGHIGHAT, Mohammad , CAO, Zhong , YUAN, Feng , LIU, Hongzhen
发明人： WU, Yong , HAGHIGHAT, Mohammad , CAO, Zhong , YUAN, Feng , LIU, Hongzhen
IPC分类号： G06F9/30
摘要： Method, systems and apparatuses may provide for technology that identifies first data and second data to be stored in a data storage. Each of the first data and the second data are in a first data format. Some technology may also interleave the first data with the second data. The interleaved first and second data are in a second data format. The second data format is different from the first data format.

6. 发明申请

WO2016154795A1 EFFICIENT ADDRESS TRANSLATION 审中-公开
标题翻译：高效地址翻译
公开(公告)号：WO2016154795A1
公开(公告)日：2016-10-06
申请号：PCT/CN2015/075219
申请日：2015-03-27
申请人： INTEL CORPORATION , ZHONG, Xueliang , WU, Yong , JIN, Yihua , LI, Jianhui , LIN, Xiaodong
发明人： ZHONG, Xueliang , WU, Yong , JIN, Yihua , LI, Jianhui , LIN, Xiaodong
IPC分类号： G06F9/45
CPC分类号： G06F12/10 , G06F9/45554 , G06F9/45558 , G06F2009/45583
摘要： One embodiment provides a device. The device includes a processor; a memory; and translator logic. The processor is to execute a host instruction set. The translator logic is to determine whether an offset is a constant and whether the offset is greater than zero and less than a maximum offset in response to receiving a guest memory access instruction that contains a base address plus or minus the offset, the maximum offset related to at least one of a host instruction set architecture (ISA) and a guest ISA.
摘要翻译：一个实施例提供了一种装置。该装置包括处理器; 记忆和翻译逻辑。处理器是执行主机指令集。翻译器逻辑是确定偏移是否为常数，以及响应于接收到包含基址加或减偏移的访客存储器访问指令，偏移量是否大于零并小于最大偏移量，相关的最大偏移量到主机指令集架构（ISA）和访客ISA中的至少一个。

7. 发明申请

WO2013104107A1 ISA BRIDGING WITH CALLBACK 审中-公开
标题翻译： ISA电话与电话
公开(公告)号：WO2013104107A1
公开(公告)日：2013-07-18
申请号：PCT/CN2012/070163
申请日：2012-01-10
申请人： INTEL CORPORATION , LI, Jianhui , LIN, Ling , WU, Yong , LIN, Xiaodong , TAN, Wen , YOUNG, Honesty Cheng , JIN, Yihua
发明人： LI, Jianhui , LIN, Ling , WU, Yong , LIN, Xiaodong , TAN, Wen , YOUNG, Honesty Cheng , JIN, Yihua
IPC分类号： G06F9/44
CPC分类号： G06F9/54 , G06F9/45504 , G06F9/541
摘要： Methods, apparatuses and storage medium associated with ISA bridging with callback, are disclosed. In various embodiments, at least one computer-readable storage medium may include instructions configured to enable a target device with a target ISA, in response to execution of the instructions, to provide an ISA bridging layer to the target device to facilitate a library service to callback a callback function of an application. The library service may be implemented for the target ISA, and the application may be implemented at least partially for a source ISA that may be different from the target ISA. The ISA bridging layer may include a source ISA emulator and a library emulator configured to cooperate to enable the application to call the library service, and the library service to callback the callback function, across the two instruction set architectures. Other embodiments may be disclosed or claimed.
摘要翻译：公开了与与回调桥接的ISA相关联的方法，装置和存储介质。在各种实施例中，至少一个计算机可读存储介质可以包括被配置为使得具有目标ISA的目标设备响应于指令的执行而向目标设备提供ISA桥接层以促进图书馆服务回调一个应用程序的回调函数。可以为目标ISA实现库服务，并且应用可以至少部分地针对可能与目标ISA不同的源ISA来实现。 ISA桥接层可以包括源ISA仿真器和库仿真器，其被配置为协作以使应用能够调用库服务，并且库服务在两个指令集体系结构之间回调回调函数。可以公开或要求保护其他实施例。

8. 发明申请

WO2021056389A1 METHODS AND APPARATUS TO PROCESS MACHINE LEARNING MODEL IN WEB-BROWSER ENVIRONMENT 审中-公开
公开(公告)号：WO2021056389A1
公开(公告)日：2021-04-01
申请号：PCT/CN2019/108439
申请日：2019-09-27
申请人： INTEL CORPORATION , LI, Jianhui , HU, Ningxin , LI, Yiqiang , WU, Yong , LUO, Yuanke
发明人： LI, Jianhui , HU, Ningxin , LI, Yiqiang , WU, Yong , LUO, Yuanke
IPC分类号： G06N3/08
摘要： Methods, apparatus, systems, and articles of manufacture to process a machine learning model in a web-browser environment are disclosed. An example apparatus includes a graph builder to accumulate machine learning operations as a graph. A tensor manager is to, in response to a request to access a tensor that is not yet available and associated with the machine learning operations, identify the graph based on the tensor. A graph cache manager is to determine whether a condensed graph corresponding to the identified graph is available. A graph condenser is to, in response to the graph cache manager determining that the condensed graph is not available, generate the condensed graph. A graph executor is to execute the condensed graph to create the tensor. The tensor manager is to provide the tensor as a response to the request to access the tensor.

9. 发明申请

WO2014022980A1 ISA BRIDGING INCLUDING SUPPORT FOR CALL TO OVERIDDING VIRTUAL FUNCTIONS 审中-公开
标题翻译： ISA桥接包括支持以覆盖虚拟功能
公开(公告)号：WO2014022980A1
公开(公告)日：2014-02-13
申请号：PCT/CN2012/079798
申请日：2012-08-08
申请人： INTEL CORPORATION , WU, Yong , LI, Jianhui , LIN, Xiaodong
发明人： WU, Yong , LI, Jianhui , LIN, Xiaodong
IPC分类号： G06F9/44
CPC分类号： G06F9/45504 , G06F9/455 , G06F9/45508 , G06F9/541
摘要： Methods, apparatuses and storage medium associated with ISA bridging with support for virtual functions, are disclosed. In embodiments, at least one computer- readable storage medium may include instructions configured to enable a target device with a target ISA, in response to execution, to provide an ISA bridging layer to the target device to facilitate a library service of a library of the target device to call a virtual function of the library, while servicing an application operating on the target device, where the application has an overriding implementation. The ISA bridging layer may include a loader configured to load the application for execution, and as part of loading the application, detect the virtual function and modify a virtual function table of the application to enable the call. Other embodiments may be disclosed or claimed.
摘要翻译：公开了与支持虚拟功能的ISA桥接相关联的方法，装置和存储介质。在实施例中，至少一个计算机可读存储介质可以包括被配置为使得具有目标ISA的目标设备响应于执行而向目标设备提供ISA桥接层以促进图书馆服务的指令目标设备调用库的虚拟功能，同时为在目标设备上运行的应用程序提供服务，其中应用程序具有重写的实现。 ISA桥接层可以包括被配置为加载应用以执行的加载器，并且作为加载应用的一部分，检测虚拟功能并修改应用的虚拟功能表以启用该呼叫。可以公开或要求保护其他实施例。

10. 发明申请

WO2013139014A1 NESTED EMULATION AND DYNAMIC LINKING ENVIRONMENT 审中-公开
标题翻译：嵌套仿真和动态链接环境
公开(公告)号：WO2013139014A1
公开(公告)日：2013-09-26
申请号：PCT/CN2012/072770
申请日：2012-03-22
申请人： INTEL CORPORATION , ZHONG, Xueliang , LI, Jianhui , CHEN, Jianping , LI, Tingtao , WU, Yong , TAN, Wen , LIN, Xiaodong
发明人： ZHONG, Xueliang , LI, Jianhui , CHEN, Jianping , LI, Tingtao , WU, Yong , TAN, Wen , LIN, Xiaodong
IPC分类号： G06F9/30
CPC分类号： G06F9/455 , G06F9/44521 , G06F9/4552
摘要： Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.
摘要翻译：各种实施例包括用于源应用和源仿真器的嵌套仿真。重复的源ISA库将源仿真器库调用重定向到目标库，从而通过第一和第二ISA之间的适当仿真通道强制本机仿真器。其他实施例涉及通过确定某些功能调用来加速动态链接，而不是通过PLT代码的仿真来处理，而是直接调用而不需要PLT代码转换。一些实施例涉及嵌套仿真和加速动态链接，但是其他实施例包括嵌套仿真和加速动态链接之一。本文描述了其它实施例。

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