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1. 发明申请

WO2016090554A1 SYSTEM AND METHOD FOR EXECUTION OF APPLICATION CODE COMPILED ACCORDING TO TWO INSTRUCTION SET ARCHITECTURES 审中-公开
标题翻译：用于执行根据两个指令集结构编译的应用代码的系统和方法
公开(公告)号：WO2016090554A1
公开(公告)日：2016-06-16
申请号：PCT/CN2014/093373
申请日：2014-12-09
申请人： INTEL CORPORATION , WU, Yong , LIN, Xiao Dong , JIN, Yihua , ZHONG, Xueliang , LI, Jianhui
发明人： WU, Yong , LIN, Xiao Dong , JIN, Yihua , ZHONG, Xueliang , LI, Jianhui
IPC分类号： G06F9/40
CPC分类号： G06F9/541 , G06F8/41 , G06F9/30145 , G06F9/4552 , G06F9/45533
摘要： Methods, apparatuses and storage medium associated with execution of application (118) code having multiple ISAs, are disclosed. In various embodiments, a runtime environment (104) may execute application (118) code having multiple instruction set architectures. The runtime environment (104) may be configured to execute first code (120) of the application (118) code according to a first instruction set architecture, while also configured to execute second code (122) of the application (118) code according to a second instruction set architecture that extends the first instruction set architecture. Using gates (124), the runtime environment (104) may be adapted to adapt an interaction from the first code (120) to the second instruction set architecture and/or adapt an interaction from the second code (122) to the first instruction set architecture and, subsequently, return to executing the application (118) code according to the first instruction set architecture or the second instruction set architecture, respectively. Other embodiments may be disclosed.
摘要翻译：公开了与执行具有多个ISA的应用程序（118）代码相关联的方法，装置和存储介质。在各种实施例中，运行时环境（104）可以执行具有多个指令集架构的应用（118）代码。运行时环境（104）可以被配置为根据第一指令集架构来执行应用程序（118）代码的第一代码（120），同时还被配置为根据应用程序（118）代码执行第二代码（122）代码扩展第一指令集架构的第二指令集体系结构。使用门（124），运行时环境（104）可以适于使来自第一代码（120）到第二指令集架构的交互和/或使从第二代码（122）到第一指令集的交互并且随后分别根据第一指令集架构或第二指令集架构返回执行应用程序（118）代码。可以公开其他实施例。

2. 发明申请

WO2016154795A1 EFFICIENT ADDRESS TRANSLATION 审中-公开
标题翻译：高效地址翻译
公开(公告)号：WO2016154795A1
公开(公告)日：2016-10-06
申请号：PCT/CN2015/075219
申请日：2015-03-27
申请人： INTEL CORPORATION , ZHONG, Xueliang , WU, Yong , JIN, Yihua , LI, Jianhui , LIN, Xiaodong
发明人： ZHONG, Xueliang , WU, Yong , JIN, Yihua , LI, Jianhui , LIN, Xiaodong
IPC分类号： G06F9/45
CPC分类号： G06F12/10 , G06F9/45554 , G06F9/45558 , G06F2009/45583
摘要： One embodiment provides a device. The device includes a processor; a memory; and translator logic. The processor is to execute a host instruction set. The translator logic is to determine whether an offset is a constant and whether the offset is greater than zero and less than a maximum offset in response to receiving a guest memory access instruction that contains a base address plus or minus the offset, the maximum offset related to at least one of a host instruction set architecture (ISA) and a guest ISA.
摘要翻译：一个实施例提供了一种装置。该装置包括处理器; 记忆和翻译逻辑。处理器是执行主机指令集。翻译器逻辑是确定偏移是否为常数，以及响应于接收到包含基址加或减偏移的访客存储器访问指令，偏移量是否大于零并小于最大偏移量，相关的最大偏移量到主机指令集架构（ISA）和访客ISA中的至少一个。

3. 发明申请

WO2013104107A1 ISA BRIDGING WITH CALLBACK 审中-公开
标题翻译： ISA电话与电话
公开(公告)号：WO2013104107A1
公开(公告)日：2013-07-18
申请号：PCT/CN2012/070163
申请日：2012-01-10
申请人： INTEL CORPORATION , LI, Jianhui , LIN, Ling , WU, Yong , LIN, Xiaodong , TAN, Wen , YOUNG, Honesty Cheng , JIN, Yihua
发明人： LI, Jianhui , LIN, Ling , WU, Yong , LIN, Xiaodong , TAN, Wen , YOUNG, Honesty Cheng , JIN, Yihua
IPC分类号： G06F9/44
CPC分类号： G06F9/54 , G06F9/45504 , G06F9/541
摘要： Methods, apparatuses and storage medium associated with ISA bridging with callback, are disclosed. In various embodiments, at least one computer-readable storage medium may include instructions configured to enable a target device with a target ISA, in response to execution of the instructions, to provide an ISA bridging layer to the target device to facilitate a library service to callback a callback function of an application. The library service may be implemented for the target ISA, and the application may be implemented at least partially for a source ISA that may be different from the target ISA. The ISA bridging layer may include a source ISA emulator and a library emulator configured to cooperate to enable the application to call the library service, and the library service to callback the callback function, across the two instruction set architectures. Other embodiments may be disclosed or claimed.
摘要翻译：公开了与与回调桥接的ISA相关联的方法，装置和存储介质。在各种实施例中，至少一个计算机可读存储介质可以包括被配置为使得具有目标ISA的目标设备响应于指令的执行而向目标设备提供ISA桥接层以促进图书馆服务回调一个应用程序的回调函数。可以为目标ISA实现库服务，并且应用可以至少部分地针对可能与目标ISA不同的源ISA来实现。 ISA桥接层可以包括源ISA仿真器和库仿真器，其被配置为协作以使应用能够调用库服务，并且库服务在两个指令集体系结构之间回调回调函数。可以公开或要求保护其他实施例。

4. 发明申请

WO2013139015A1 HYBRID EMULATION AND KERNEL FUNCTION PROCESSING SYSTEMS AND METHODS 审中-公开
标题翻译：混合仿真和KERNEL函数处理系统和方法
公开(公告)号：WO2013139015A1
公开(公告)日：2013-09-26
申请号：PCT/CN2012/072780
申请日：2012-03-22
申请人： INTEL CORPORATION , LIN, Xiaodong , JIN, Yihua , WU, Yong , LI, Jianhui , LIN, Ling , SHI, Xingdong
发明人： LIN, Xiaodong , JIN, Yihua , WU, Yong , LI, Jianhui , LIN, Ling , SHI, Xingdong
IPC分类号： G06F9/45
CPC分类号： G06F9/4552
摘要： One embodiment pre-builds translations of kernel functions (KFs) and loads them into a translation pool and corresponding indexed table. The KFs are thus quickly loaded and do not necessarily await trapping and emulation via a LIB emulator. This results in faster access to KFs. Other embodiments provide hybrid emulation where some application functions (e.g., those that need quick performance) are translated from a source ISA library while other applications functions are processed via emulation to a target ISA library. Doing so provides faster access to certain functions. Other embodiments are described herein.
摘要翻译：一个实施例预先构建内核函数（KF）的翻译，并将它们加载到转换池和相应的索引表中。因此，KF快速加载，并且不一定等待通过LIB仿真器进行捕获和仿真。这样可以更快地访问KF。其他实施例提供混合仿真，其中一些应用功能（例如，需要快速性能的那些）从源ISA库转换，而其他应用功能通过仿真被处理到目标ISA库。这样做可以更快地访问某些功能。本文描述了其它实施例。

5. 发明申请

WO2014047828A1 METHOD AND APPARATUS TO SCHEDULE STORE INSTRUCTIONS ACROSS ATOMIC REGIONS IN BINARY TRANSLATION 审中-公开
标题翻译：方法和装置在二进制翻译中按照原子地区安排存储指令
公开(公告)号：WO2014047828A1
公开(公告)日：2014-04-03
申请号：PCT/CN2012/082139
申请日：2012-09-27
申请人： INTEL CORPORATION , MA, Guokai , JIN, Yihua , LAVERY, Daniel M. , LI, Jianhui
发明人： MA, Guokai , JIN, Yihua , LAVERY, Daniel M. , LI, Jianhui
IPC分类号： G06F9/30
CPC分类号： G06F8/52 , G06F9/30 , G06F9/30065 , G06F9/3834 , G06F9/3857
摘要： A method and system to support scheduling of memory store instructions across atomic regions in binary translation in a processing unit or processor. In one embodiment of the invention, the processing unit has a store buffer that allows store instructions to be issued in different order than the source binary program order but still retire in source binary program order. This facilitates a small atomic region that maps to each iteration of a source binary code and these atomic regions are joined together into a pipelined region. In one embodiment of the invention, the processing unit executes commit instruction(s) once every loop iteration instead of executing the commit instruction(s) once after the loop exit.
摘要翻译：一种支持在处理单元或处理器中的二进制转换中跨原子区域的存储器存储指令调度的方法和系统。在本发明的一个实施例中，处理单元具有存储缓冲器，其允许以与源二进制程序顺序不同的顺序发布存储指令，但仍然以源二进制程序顺序退出。这有助于映射到源二进制代码的每个迭代的小原子区域，并且这些原子区域被连接在一起成流水线区域。在本发明的一个实施例中，处理单元每循环迭代执行一次提交指令，而不是在循环退出之后执行一次提交指令。

6. 发明申请

WO2015070440A1 SEAMLESS HOST SYSTEM GESTURE EXPERIENCE FOR GUEST APPLICATIONS ON TOUCH BASED DEVICES 审中-公开
标题翻译：无缝主机系统针对基于触摸的设备应用的体验
公开(公告)号：WO2015070440A1
公开(公告)日：2015-05-21
申请号：PCT/CN2013/087244
申请日：2013-11-15
申请人： INTEL CORPORATION
发明人： JIN, Yihua , LI, Jianhui , LI, Tingtao , LIN, Xiaodong
IPC分类号： G06F3/041
CPC分类号： G06F9/445 , G06F3/04883 , G06F9/451 , G06F9/45545
摘要： Methods and apparatus relating to seamless host system gesture experience for guest applications on touch based devices are described. In an embodiment, Host Gesture Capture (HGC) logic detects a gesture in response to a touch event. The HGC logic forwards the gesture to Host Gesture Emulator (HGE) logic in response to a determination that the gesture is unrelated to an operation of a host system. The HGE logic operates in accordance with a guest operating system of the host system. Other embodiments are also claimed and described.
摘要翻译：描述与基于触摸的设备上的访客应用的无缝主机系统手势体验相关的方法和装置。在一个实施例中，主机手势捕获（HGC）逻辑检测响应于触摸事件的手势。响应于确定手势与主机系统的操作无关，HGC逻辑将手势转发到主机手势仿真器（HGE）。 HGE逻辑根据主机系统的客户操作系统进行操作。还要求保护和描述其它实施例。

7. 发明公开

EP3069217A1 SEAMLESS HOST SYSTEM GESTURE EXPERIENCE FOR GUEST APPLICATIONS ON TOUCH BASED DEVICES 无效
标题翻译： NAHTLOSE HOSTSYSTEM-GESTENERFAHRUNGFÜRGASTANWENDUNGEN AUFBERÜHRUNGSEMPFINDLICHENVORRICHTUNGEN
公开(公告)号：EP3069217A1
公开(公告)日：2016-09-21
申请号：EP13897583.4
申请日：2013-11-15
申请人： Intel Corporation
发明人： JIN, Yihua , LI, Jianhui , LI, Tingtao , LIN, Xiaodong
IPC分类号： G06F3/041
CPC分类号： G06F9/445 , G06F3/04883 , G06F9/451 , G06F9/45545
摘要： Methods and apparatus relating to seamless host system gesture experience for guest applications on touch based devices are described. In an embodiment, Host Gesture Capture (HGC) logic detects a gesture in response to a touch event. The HGC logic forwards the gesture to Host Gesture Emulator (HGE) logic in response to a determination that the gesture is unrelated to an operation of a host system. The HGE logic operates in accordance with a guest operating system of the host system. Other embodiments are also claimed and described.
摘要翻译：描述与基于触摸的设备上的访客应用的无缝主机系统姿态体验有关的方法和装置。在一个实施例中，主机手势捕获（HGC）逻辑检测响应于触摸事件的手势。响应于确定手势与主机系统的操作无关，HGC逻辑将手势转发到主机手势仿真器（HGE）。 HGE逻辑根据主机系统的客户机操作系统进行操作。还要求保护和描述其它实施例。

8. 发明公开

EP3230853A1 SYSTEM AND METHOD FOR EXECUTION OF APPLICATION CODE COMPILED ACCORDING TO TWO INSTRUCTION SET ARCHITECTURES 审中-公开
标题翻译：用于执行根据两个指令集体系结构编译的应用代码的系统和方法
公开(公告)号：EP3230853A1
公开(公告)日：2017-10-18
申请号：EP14907858.6
申请日：2014-12-09
申请人： Intel Corporation
发明人： WU, Yong , LIN, Xiao Dong , JIN, Yihua , ZHONG, Xueliang , LI, Jianhui
IPC分类号： G06F9/40
CPC分类号： G06F9/541 , G06F8/41 , G06F9/30145 , G06F9/4552 , G06F9/45533
摘要： Methods, apparatuses and storage medium associated with execution of application code having multiple ISAs, are disclosed. In various embodiments, a runtime environment may execute application code having multiple instruction set architectures. The runtime environment may be configured to execute first code of the application code according to a first instruction set architecture, while also configured to execute second code of the application code according to a second instruction set architecture that extends the first instruction set architecture. Using gates, the runtime environment may be adapted to adapt an interaction from the first code to the second instruction set architecture and/or adapt an interaction from the second code to the first instruction set architecture and, subsequently, return to executing the application code according to the first instruction set architecture or the second instruction set architecture, respectively. Other embodiments may be disclosed or claimed.
摘要翻译：公开了与执行具有多个ISA的应用程序（118）代码相关联的方法，设备和存储介质。在各种实施例中，运行时环境（104）可以执行具有多个指令集体系结构的应用程序（118）代码。运行时环境（104）可以被配置为根据第一指令集架构执行应用程序（118）代码的第一代码（120），同时还被配置为执行应用程序（118）代码的第二代码（122）扩展第一指令集体系结构的第二指令集体系结构。使用门（124），运行时间环境（104）可适用于适配从第一代码（120）到第二指令集架构的交互和/或适配来自第二代码（122）到第一指令集架构，并且随后分别根据第一指令集架构或第二指令集架构返回执行应用程序（118）代码。其他实施例可以被公开。

9. 发明授权

EP2802983B1 ISA BRIDGING WITH CALLBACK 有权
标题翻译： ISA与回调桥接
公开(公告)号：EP2802983B1
公开(公告)日：2016-12-14
申请号：EP12865442.3
申请日：2012-01-10
申请人： Intel Corporation
发明人： LI, Jianhui , LIN, Ling , WU, Yong , LIN, Xiaodong , TAN, Wen , YOUNG, Honesty Cheng , JIN, Yihua
IPC分类号： G06F9/44 , G06F9/455 , G06F9/54
CPC分类号： G06F9/54 , G06F9/45504 , G06F9/541

10. 发明公开

EP3274824A1 EFFICIENT ADDRESS TRANSLATION 有权
标题翻译：有效的地址翻译
公开(公告)号：EP3274824A1
公开(公告)日：2018-01-31
申请号：EP15886782.0
申请日：2015-03-27
申请人： Intel Corporation
发明人： ZHONG, Xueliang , WU, Yong , JIN, Yihua , LI, Jianhui , LIN, Xiaodong
IPC分类号： G06F9/45
CPC分类号： G06F12/10 , G06F9/30174 , G06F9/355 , G06F9/45554 , G06F9/45558 , G06F2009/45583
摘要： One embodiment provides a device. The device includes a processor; a memory; and translator logic. The processor is to execute a host instruction set. The translator logic is to determine whether an offset is a constant and whether the offset is greater than zero and less than a maximum offset in response to receiving a guest memory access instruction that contains a base address plus or minus the offset, the maximum offset related to at least one of a host instruction set architecture (ISA) and a guest ISA.

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