专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2015069235A1 VIRTUAL RETRY QUEUE 审中-公开
标题翻译：虚拟重试队列
公开(公告)号：WO2015069235A1
公开(公告)日：2015-05-14
申请号：PCT/US2013/068734
申请日：2013-11-06
申请人： INTEL CORPORATION , FAHIM, Bahaa , LIU, Yen-Cheng , CHAMBERLAIN, Jeffrey D.
发明人： FAHIM, Bahaa , LIU, Yen-Cheng , CHAMBERLAIN, Jeffrey D.
IPC分类号： G06F13/00 , G06F9/44
CPC分类号： G06F9/52
摘要： A starvation mode is entered and a particular dependency of a first request in a retry queue is identified. The particular dependency is determined to be acquired and the first request is retried based on acquisition of the particular dependency.
摘要翻译：
进入饥饿模式并识别重试队列中第一请求的特定依赖性。确定要获取特定的依赖关系，并根据获取的特定依赖关系重试第一个请求。

2. 发明申请

WO2013103347A1 IMPROVING VALUE OF FORWARD STATE BY INCREASING LOCAL CACHING AGENT FORWARDING 审中-公开
标题翻译：通过增加本地高速缓存代理来改善前进状态的价值
公开(公告)号：WO2013103347A1
公开(公告)日：2013-07-11
申请号：PCT/US2012/020408
申请日：2012-01-06
申请人： INTEL CORPORATION , GEETHA, Vedaraman , CHAMBERLAIN, Jeffrey D. , KOTTAPALLI, Sailesh , KUMAR, Ganesh , NEEFS, Henk G. , ACHTMAN, Neil J. , JUNG, Bongjin
发明人： GEETHA, Vedaraman , CHAMBERLAIN, Jeffrey D. , KOTTAPALLI, Sailesh , KUMAR, Ganesh , NEEFS, Henk G. , ACHTMAN, Neil J. , JUNG, Bongjin
IPC分类号： G06F13/14 , G06F13/38 , G06F9/06
CPC分类号： G06F12/0817 , G06F12/084 , G06F2212/622
摘要： Methods and apparatus relating to improving the value of F-state by increasing a local caching agent's data forwarding are described. In one embodiment, the opportunity for forwarding from a local caching agent is improved by allowing the local caching agent to keep an F-state copy of the line while sending an S-state copy to the requestor (e.g., in response to a non-ownership read operation). Other embodiments are also disclosed.
摘要翻译：描述了通过增加本地缓存代理的数据转发来提高F状态的价值的方法和装置。在一个实施例中，通过允许本地缓存代理在向请求者发送S状态副本的同时保留该行的F状态副本（例如，响应于非本地缓存代理）而改进来自本地缓存代理的转发的机会，所有权读取操作）。还公开了其他实施例。

3. 发明申请

WO2016160202A1 TWO LEVEL MEMORY FULL LINE WRITES 审中-公开
标题翻译：两级记忆全线写
公开(公告)号：WO2016160202A1
公开(公告)日：2016-10-06
申请号：PCT/US2016/019698
申请日：2016-02-26
申请人： INTEL CORPORATION
发明人： BLANKENSHIP, Robert G. , CHAMBERLAIN, Jeffrey D. , LIU, Yen-Cheng , GEETHA, Vedaraman
IPC分类号： G06F12/08 , G06F12/02 , G06F13/16
CPC分类号： G06F12/0891 , G06F12/0808 , G06F12/0831 , G06F12/0893 , G06F12/126 , G06F2212/1016
摘要： A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.
摘要翻译：存储器控制器接收存储器无效请求，该存储器无效请求引用具有远存储器和近存储器的两级系统存储器拓扑中的远存储器行，识别对应于该行的近存储器的地址，并且在地址处读取数据以确定是否该行的副本在近内存中。如果数据包含远端存储器的另一行的副本，而另一行的副本是脏的，则该地址的数据将被刷新到远端存储器。发送内存无效请求的完成以指示相干代理被授予对该行的独占访问权限。通过独占访问，将修改该行以生成行的修改版本，并且将使用修改版本的行覆盖近端存储器的地址。

4. 发明申请

WO2015048826A1 SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WRITES TO AN ADDRESS 审中-公开
标题翻译：规范机制，以实施向地址写入的监视器的指令
公开(公告)号：WO2015048826A1
公开(公告)日：2015-04-02
申请号：PCT/US2014/059130
申请日：2014-10-03
申请人： INTEL CORPORATION
发明人： LIU, Yen-Cheng , FAHIM, Bahaa , HALLNOR, Erik G. , CHAMBERLAIN, Jeffrey D. , VAN DOREN, Stephen R. , JUAN, Antonio
IPC分类号： G06F11/30 , G06F12/06
CPC分类号： G06F12/084 , G06F9/30087 , G06F9/3009 , G06F9/46 , G06F12/0811 , G06F12/0833 , G06F12/0846 , G06F2212/1016
摘要： A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.
摘要翻译：处理器包括对应于分布式高速缓存的第一高速缓存部分的高速缓存器侧地址监视器单元，其具有小于处理器的逻辑处理器总数的高速缓存器侧地址监视器存储位置的总数。每个缓存侧地址监视器存储位置是存储要监视的地址。核心侧地址监视器单元对应于第一核心，并且具有与第一核心的多个逻辑处理器相同数量的核心侧地址监视器存储位置。每个核心侧地址监视器存储位置用于存储第一核心的不同对应逻辑处理器的地址和监视状态。高速缓存侧地址监视器存储溢出单元对应于第一高速缓存部分，并且当没有未使用的高速缓存侧地址监视器存储位置可用于存储要监视的地址时，强制执行地址监视器存储溢出策略。

5. 发明申请

WO2020096639A1 FUNCTION AS A SERVICE (FAAS) SYSTEM ENHANCEMENTS 审中-公开
公开(公告)号：WO2020096639A1
公开(公告)日：2020-05-14
申请号：PCT/US2019/027659
申请日：2019-04-16
申请人： INTEL CORPORATION
发明人： HAGHIGHAT, Mohammad R. , DOSHI, Kshitij , HERDRICH, Andrew J. , MOHAN, Anup , IYER, Ravishankar R. , SUN, Mingqiu , BHUYAN, Krishna , GOH, Teck Joo , KUMAR, Mohan J. , PRINKE, Michael , LEMAY, Michael , PELED, Leeor , TSAI, Jr-Shian , DURHAM, David M. , CHAMBERLAIN, Jeffrey D. , SUKHOMLINOV, Vadim A. , DAHLEN, Eric J. , BAGHSORKHI, Sara , SANE, Harshad , MELIK-ADAMYAN, Areg , SAHITA, Ravi , BABOKIN, Dmitry Yurievich , STEINER, Ian M. , BACHMUTSKY, Alexander , RAO, Anil , ZHANG, Mingwei , JAIN, Nilesh K. , FIROOZSHAHIAN, Amin , PATEL, Baiju V. , HUANG, Wenyong , RAGHURAM, Yeluri
IPC分类号： G06F9/50 , G06F11/30
摘要： Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution. Furthermore, the computing system enables customers to pay only when their code gets executed with a granular billing down to millisecond increments.

6. 发明申请

WO2021247077A1 LINK AFFINITIZATION TO REDUCE TRANSFER LATENCY 审中-公开
公开(公告)号：WO2021247077A1
公开(公告)日：2021-12-09
申请号：PCT/US2020/064654
申请日：2020-12-11
申请人： INTEL CORPORATION
发明人： MATHEW ABRAHAM, Vinit , CHAMBERLAIN, Jeffrey D. , LIU, Yen-Cheng , NALLUSAMY, Eswaramoorthi , EACHEMPATI, Soumya S.
IPC分类号： G06F12/0802 , G06F13/40 , G06F13/16 , G06F12/0824 , G06F12/0826 , G06F13/1668 , G06F13/4027 , G06F2212/1024 , G06F2213/16 , G06F2213/40
摘要： Examples described herein relate to processor circuitry to issue a cache coherence message to a central processing unit (CPU) cluster by selection of a target cluster and issuance of the request to the target cluster, wherein the target cluster comprises the cluster or the target cluster is directly connected to the cluster. In some examples, the selected target cluster is associated with a minimum number of die boundary traversals. In some examples, the processor circuitry is to read an address range for the cluster to identify the target cluster using a single range check over memory regions including local and remote clusters. In some examples, issuance of the cache coherence message to a cluster is to cause the cache coherence message to traverse one or more die interconnections to reach the target cluster.

8. 发明申请

WO2022093440A1 CACHE LINE DEMOTE INFRASTRUCTURE FOR MULTI-PROCESSOR PIPELINES 审中-公开
公开(公告)号：WO2022093440A1
公开(公告)日：2022-05-05
申请号：PCT/US2021/051360
申请日：2021-09-21
申请人： INTEL CORPORATION
发明人： SHAH, Rahul R. , MASLEKAR, Omkar , AUTEE, Priya , VERPLANKE, Edwin , HERDRICH, Andrew J. , CHAMBERLAIN, Jeffrey D.
IPC分类号： G06F12/0811 , G06F12/084 , G06F9/30 , G06F12/1009
摘要： Examples described herein relate to a manner of demoting multiple cache lines to shared memory. In some examples, a shared cache is accessible by at least two processor cores and a region of the cache is larger than a cache line and is designated for demotion from the cache to the shared cache. In some examples, the cache line corresponds to a memory address in a region of memory. In some examples, an indication that the region of memory is associated with a cache line demote operation is provided in an indicator in a page table entry (PTE). In some examples, the indication that the region of memory is associated with a cache line demote operation is based on a command in an application executed by a processor. In some examples, the cache is an level 1 (L1) or level 2 (L2) cache.

9. 发明申请

WO2018071368A1 MULTIPLE DIES HARDWARE PROCESSORS AND METHODS 审中-公开
标题翻译：多模块硬件处理器和方法
公开(公告)号：WO2018071368A1
公开(公告)日：2018-04-19
申请号：PCT/US2017/055849
申请日：2017-10-10
申请人： INTEL CORPORATION
发明人： NASSIF, Nevine , LIU, Yen-Cheng , SISTLA, Krishnakanth V. , PASDAST, Gerald , EACHEMPATI, Siva Soumya , SINGH, Tejpal , VARMA, Ankush , KUMASHIKAR, Mahesh K. , NIMMAGADDA, Srikanth , MOLNAR, Carleton L. , GEETHA, Vedaraman , CHAMBERLAIN, Jeffrey D. , HALLECK, William R. , CHRYSOS, George Z. , AYERS, John R. , SUBBAREDDY, Dheeraj R.
IPC分类号： G06F13/40
CPC分类号： G06F15/7889 , G06F1/10 , G06F9/3869 , G06F9/5038 , G06F15/167 , G06F15/17312
摘要： Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
摘要翻译：描述了涉及具有多个互连管芯的硬件处理器的方法和设备。在一个实施例中，硬件处理器包括多个物理上分离的管芯以及将多个物理上分离的管芯电耦合在一起的互连。在另一个实施例中，用于创建硬件处理器的方法包括提供多个物理上分离的管芯，并且用互连将多个物理上分离的管芯电耦合在一起。

10. 发明申请

WO2016153726A1 A METHOD, APPARATUS AND SYSTEM FOR OPTIMIZING CACHE MEMORY TRANSACTION HANDLING IN A PROCESSOR 审中-公开
标题翻译：用于优化处理器中的高速缓存存储器交易处理的方法，装置和系统
公开(公告)号：WO2016153726A1
公开(公告)日：2016-09-29
申请号：PCT/US2016/020013
申请日：2016-02-29
申请人： INTEL CORPORATION
发明人： FAHIM, Bahaa , LIU, Yen-Cheng , GEETHA, Vedaraman , CHAMBERLAIN, Jeffrey D. , HUANG, Min
IPC分类号： G06F15/173 , G06F12/08 , G06F12/02
CPC分类号： G06F12/0855 , G06F12/0817 , G06F12/0831 , G06F2212/27 , G06F2212/621 , Y02D10/13
摘要： In one embodiment, a processor includes a caching home agent (CHA) coupled to a core and a cache memory and includes a cache controller having a cache pipeline and a home agent having a home agent pipeline. The CHA may: receive, in the home agent pipeline, information from an external agent responsive to a miss for data in the cache memory; issue a global ordering signal from the home agent pipeline to a requester of the data to inform the requester of receipt of the data; and report issuance of the global ordering signal to the cache pipeline, to prevent the cache pipeline from issuance of a global ordering signal to the requester. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括耦合到核心和高速缓冲存储器的缓存归属代理（CHA），并且包括具有高速缓存流水线和具有归属代理流水线的归属代理的高速缓存控制器。 CHA可以：在归属代理流程中接收来自外部代理的响应于高速缓冲存储器中的数据的遗漏的信息; 从归属代理流水线向数据的请求者发出全局排序信号，以通知请求者接收数据; 并向缓存流水线报告全局排序信号的发布，以防止缓存流水线向请求者发出全局排序信号。描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式