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1. 发明申请

WO2017165050A1 BI-DIRECTIONAL MULTI-MODE CHARGE PUMP 审中-公开
标题翻译：双向多模式电荷泵
公开(公告)号：WO2017165050A1
公开(公告)日：2017-09-28
申请号：PCT/US2017/018859
申请日：2017-02-22
申请人： INTEL CORPORATION
发明人： KULKARNI, Jaydeep , SHIM, Yong , MEINERZHAGEN, Pascal A. , KHELLAH, Muhammad M.
IPC分类号： H02M3/07
摘要： Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.
摘要翻译：一些实施例包括使用耦合到第一供电节点和第二供电节点的电荷泵的装置和方法。电荷泵被布置成在第一时间间隔期间将电荷从第一供电节点传递到第二供电节点，并且在第二时间间隔期间将电荷从第二供电节点传递到第一供电节点。

2. 发明申请

WO2017083019A1 REGISTER FILES INCLUDING DISTRIBUTED CAPACITOR CIRCUIT BLOCKS 审中-公开
标题翻译：寄存器文件，包括分布式电容电路块
公开(公告)号：WO2017083019A1
公开(公告)日：2017-05-18
申请号：PCT/US2016/053390
申请日：2016-09-23
申请人： INTEL CORPORATION
发明人： BONAKDAR, Hamid-Reza S. , KULKARNI, Jaydeep
IPC分类号： G11C11/401 , G06F12/02
CPC分类号： G11C5/025 , G11C5/063 , G11C5/10 , G11C7/00 , G11C7/12 , G11C7/14 , G11C7/227 , G11C8/08 , G11C8/14 , G11C11/418
摘要： Some embodiments include apparatuses having a first node to receive a supply voltage, a second node, a switching circuit to couple the first node to the second node and to decouple the first node from the second node, circuit blocks coupled to the second node and the switching circuit, and drivers coupled to the second node. Each of the circuit blocks includes a capacitor having a plate coupled to the second node. Each of the drivers is associated with a conductive line. The conductive line is associated with memory cells.
摘要翻译：一些实施例包括具有接收电源电压的第一节点，第二节点，将第一节点耦合到第二节点并将第一节点与第二节点解耦的装置，电路耦合到第二节点和开关电路的块，以及耦合到第二节点的驱动器。每个电路块包括具有耦合到第二节点的板的电容器。每个驱动器都与导电线相关联。导线与存储单元相关联。

3. 发明申请

WO2016209540A1 CAPACITIVE WORDLINE BOOSTING 审中-公开
标题翻译：电容词加强
公开(公告)号：WO2016209540A1
公开(公告)日：2016-12-29
申请号：PCT/US2016/034437
申请日：2016-05-26
申请人： INTEL CORPORATION
发明人： KULKARNI, Jaydeep , KOLAR, Pramod , SHARMA, Ankit , CHATTERJEE, Subho , SUBRAMANIAN, Karthik , SHEIKH, Farhana , MA, Wei-Hsiang
IPC分类号： G11C5/14 , G11C8/08
CPC分类号： G11C8/08 , G11C5/145 , G11C7/18 , G11C11/413 , G11C11/418 , G11C11/419
摘要： In some embodiments, disclosed is a wordline boosting technique using a self-timed capacitive charge boosting approach.
摘要翻译：在一些实施例中，公开了使用自定时电容性电荷增压方法的字线增强技术。

4. 发明申请

WO2017111881A1 FAST FOURIER TRANSFORM ARCHITECTURE 审中-公开
标题翻译：快速傅立叶变换结构
公开(公告)号：WO2017111881A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/066963
申请日：2015-12-21
申请人： INTEL CORPORATION
发明人： SHEIKH, Farhana , SHARMA, Ankit , KULKARNI, Jaydeep
IPC分类号： H04L27/26 , G06F17/14
CPC分类号： H04L27/263 , G06F17/142
摘要： A calculation circuit for calculating a transform of an input sequence may include a plurality of butterfly computation circuits configured to perform a plurality of butterfly computations and to produce a plurality of outputs during each of a plurality of computation stages, a wired routing network configured to route a first plurality of outputs of the plurality of butterfly computation circuits from a first computation stage of the plurality of computation stages as input to the plurality of butterfly computation circuits during a second computation stage of the plurality of computation stages according to a reconfigurable routing configuration, and routing control circuitry configured to modify the reconfigurable routing configuration for a third computation stage of the plurality of computation stages.
摘要翻译：用于计算输入序列的变换的计算电路可以包括多个蝶形运算电路，该多个蝶形运算电路被配置为执行多个蝶形运算并且在多个计算阶段中的每一个阶段期间产生多个输出有线路由网络，其被配置为在多个计算级的第一计算级期间将多个计算级中的第一计算级的第一多个输出作为输入发送到多个蝶形计算电路根据可重新配置的路由配置来执行阶段;以及路由控制电路，其被配置为修改用于所述多个计算阶段中的第三计算阶段的可重新配置路由配置。

5. 发明申请

WO2017052904A1 MEMORY DEVICE INCLUDING ENCODED DATA LINE-MULTIPLEXER 审中-公开
标题翻译：包含编码数据线路多路复用器的存储器件
公开(公告)号：WO2017052904A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/048234
申请日：2016-08-23
申请人： INTEL CORPORATION
发明人： KULKARNI, Jaydeep
IPC分类号： G11C16/26 , G11C16/08 , G11C16/04 , G11C8/10
CPC分类号： G11C7/12 , G11C7/1048 , G11C8/08 , G11C8/10 , G11C17/12 , G11C2207/005
摘要： Some embodiments include apparatuses and methods having non-volatile memory cells, a data line associated with a group of non-volatile memory cells of the non-volatile memory cells, a first transistor coupled to the data line and a node, a second transistor coupled to the node and an additional node, a pull-up component coupled to the node and a supply node, and an additional pull-up component coupled to the additional node and the supply node.
摘要翻译：一些实施例包括具有非易失性存储器单元的装置和方法，与非易失性存储单元的一组非易失性存储单元相关联的数据线，耦合到该数据线和一个节点的第一晶体管，耦合到第二晶体管的第二晶体管所述节点和附加节点，耦合到所述节点和供应节点的上拉组件以及耦合到所述附加节点和所述供应节点的附加上拉组件。

6. 发明申请

WO2013089698A1 MULTI-SUPPLY SEQUENTIAL LOGIC UNIT 审中-公开
标题翻译：多供应序列逻辑单元
公开(公告)号：WO2013089698A1
公开(公告)日：2013-06-20
申请号：PCT/US2011/064848
申请日：2011-12-14
申请人： INTEL CORPORATION , RAYCHOWDHURY, Arijit , KULKARNI, Jaydeep , TSCHANZ, James W.
发明人： RAYCHOWDHURY, Arijit , KULKARNI, Jaydeep , TSCHANZ, James W.
IPC分类号： G06F1/04 , G06F1/26
CPC分类号： H03K19/017509 , G06F1/10 , G06F1/3296 , Y02D10/172
摘要： Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.
摘要翻译：这里描述了用于减少处理器中的顺序逻辑单元的时钟到输出延迟的装置，方法和系统。所述装置包括顺序单元，包括：数据路径，用于接收包括在第一电源电平上操作的逻辑门的输入信号，所述数据路径以产生输出信号; 以及时钟路径，包括用于在第二电源电平上操作的逻辑门，所述时钟路径的逻辑门使用采样信号对所述输入信号进行采样以产生所述输出信号，其中所述第二电源电平高于所述第一电力供应水平。该装置改善（即减少）顺序单元的建立时间，并允许处理器以最小工作电压（Vmin）运行，而不降低顺序单元的性能。

7. 发明公开

EP3433923A1 BI-DIRECTIONAL MULTI-MODE CHARGE PUMP 有权
公开(公告)号：EP3433923A1
公开(公告)日：2019-01-30
申请号：EP17770792.4
申请日：2017-02-22
申请人： Intel Corporation
发明人： KULKARNI, Jaydeep , SHIM, Yong , MEINERZHAGEN, Pascal A. , KHELLAH, Muhammad M.
IPC分类号： H02M3/07

8. 发明公开

EP3607415A1 ADAPTIVE VOLTAGE SYSTEM FOR AGING GUARD-BAND REDUCTION 审中-公开
公开(公告)号：EP3607415A1
公开(公告)日：2020-02-12
申请号：EP18781356.3
申请日：2018-03-02
申请人： Intel Corporation
发明人： CHO, Minki , KULKARNI, Jaydeep , TOKUNAGA, Carlos , KHELLAH, Muhammad , TSCHANZ, James
IPC分类号： G06F1/26 , G06F1/32

9. 发明公开

EP3314610A1 CAPACITIVE WORDLINE BOOSTING 审中-公开
标题翻译：电容式字库提升
公开(公告)号：EP3314610A1
公开(公告)日：2018-05-02
申请号：EP16814985.4
申请日：2016-05-26
申请人： Intel Corporation
发明人： KULKARNI, Jaydeep , KOLAR, Pramod , SHARMA, Ankit , CHATTERJEE, Subho , SUBRAMANIAN, Karthik , SHEIKH, Farhana , MA, Wei-Hsiang
IPC分类号： G11C5/14 , G11C8/08
CPC分类号： G11C8/08 , G11C5/145 , G11C7/18 , G11C11/413 , G11C11/418 , G11C11/419
摘要： In some embodiments, disclosed is a wordline boosting technique using a self-timed capacitive charge boosting approach.

10. 发明授权

EP2791753B1 MULTI-SUPPLY SEQUENTIAL LOGIC UNIT 有权转让
标题翻译：多电源连续逻辑单元
公开(公告)号：EP2791753B1
公开(公告)日：2017-10-04
申请号：EP11877465.2
申请日：2011-12-14
申请人： Intel Corporation
发明人： RAYCHOWDHURY, Arijit , KULKARNI, Jaydeep , TSCHANZ, James W.
IPC分类号： G06F1/04 , G06F1/26 , G06F1/32
CPC分类号： H03K19/017509 , G06F1/10 , G06F1/3296 , Y02D10/172
摘要： Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.
摘要翻译：这里描述的是用于降低处理器中时序逻辑单元的时钟到输出延迟的装置，方法和系统。该装置包括顺序单元，该顺序单元包括：数据路径，用于接收输入信号，该输入信号包括在第一电源电平上操作的逻辑门，该数据路径用于生成输出信号; 以及包括逻辑门以在第二电源电平上操作的时钟路径，所述时钟路径的逻辑门用采样信号采样所述输入信号以生成所述输出信号，其中所述第二电源电平高于所述第一电源供应水平。该装置改进（即减少）顺序单元的建立时间，并允许处理器在最小工作电压（Vmin）下工作，而不降低顺序单元的性能。

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