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1. 发明申请

WO2009079159A2 SYSTEMS AND METHODS TO INCREASE UNIAXIAL COMPRESSIVE STRESS IN TRI-GATE TRANSISTORS 审中-公开
标题翻译：用于增加三栅极晶体管中的单轴压缩应力的系统和方法
公开(公告)号：WO2009079159A2
公开(公告)日：2009-06-25
申请号：PCT/US2008084344
申请日：2008-11-21
申请人： INTEL CORP , RAKSHIT TITASH , GILES MARTIN D , GHANI TAHIR , MURTHY ANAND , CEA STEPHEN M
发明人： RAKSHIT TITASH , GILES MARTIN D , GHANI TAHIR , MURTHY ANAND , CEA STEPHEN M
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/823437 , H01L21/26506 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A transistor structure that increases uniaxial compressive stress on the channel region of a tri-gate transistor comprises at least two semiconductor bodies formed on a substrate, each semiconductor body having a pair of laterally opposite sidewalls and a top surface, a common source region formed on one end of the semiconductor bodies, wherein the common source region is coupled to all of the at least two semiconductor bodies, a common drain region formed on another end of the semiconductor bodies, wherein the common drain region is coupled to all of the at least two semiconductor bodies, and a common gate electrode formed over the at least two semiconductor bodies, wherein the common gate electrode provides a gate electrode for each of the at least two semiconductor bodies and wherein the common gate electrode has a pair of laterally opposite sidewalls that are substantially perpendicular to the sidewalls of the semiconductor bodies.
摘要翻译：一种增加三栅极晶体管的沟道区上的单轴压缩应力的晶体管结构包括至少两个形成在衬底上的半导体本体，每个半导体本体具有一对横向相对的侧壁和顶表面，形成在其上的公共源极区半导体本体的一端，其中公共源极区域耦合到所有至少两个半导体本体;公共漏极区域，形成在半导体本体的另一端上，其中公共漏极区域耦合到所有的至少一个两个半导体本体以及形成在所述至少两个半导体本体上方的公共栅电极，其中所述公共栅电极为所述至少两个半导体本体中的每一个提供栅电极，并且其中所述公共栅电极具有一对横向相对的侧壁，基本垂直于半导体本体的侧壁。

2. 发明申请

WO2012040075A3 NON-PLANAR DEVICE HAVING UNIAXIALLY STRAINED FIN AND METHOD OF MAKING SAME 审中-公开
标题翻译：具有非均匀应变FIN的非平面设备及其制造方法
公开(公告)号：WO2012040075A3
公开(公告)日：2012-06-07
申请号：PCT/US2011052084
申请日：2011-09-19
申请人： INTEL CORP , CEA STEPHEN M , KOTLYAR ROZA , KAVALIEROS JACK T , GILES MARTIN D , GHANI TAHIR , KUHN KELIN J , KUHN MARKUS , ZELICK NANCY M
发明人： CEA STEPHEN M , KOTLYAR ROZA , KAVALIEROS JACK T , GILES MARTIN D , GHANI TAHIR , KUHN KELIN J , KUHN MARKUS , ZELICK NANCY M
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/1054 , H01L29/66795 , H01L29/7849 , H01L29/785
摘要： A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.
摘要翻译：根据该方法制造的方法和装置。该方法包括提供包括第一材料的基底，并且提供包括第二材料的翅片，所述翅片设置在所述基底上并且具有器件活性部分，所述第一材料和所述第二材料在其各自的结晶结构之间呈现晶格失配。提供散热片包括在基板上提供包括第二材料的双轴应变膜; 并除去双轴应变膜的部分以形成基本上单轴应变的翅片。

3. 发明申请

WO2012087581A3 TRANSISTORS WITH HIGH CONCENTRATION OF BORON DOPED GERMANIUM 审中-公开
标题翻译：高浓度硼掺杂锗的晶体管
公开(公告)号：WO2012087581A3
公开(公告)日：2012-09-07
申请号：PCT/US2011063813
申请日：2011-12-07
申请人： INTEL CORP , MURTHY ANAND S , GLASS GLENN A , GHANI TAHIR , PILLARISETTY RAVI , MUKHERJEE NILOY , KAVALIEROS JACK T , KOTLYAR ROZA , RACHMADY WILLY , LIU MARK Y
发明人： MURTHY ANAND S , GLASS GLENN A , GHANI TAHIR , PILLARISETTY RAVI , MUKHERJEE NILOY , KAVALIEROS JACK T , KOTLYAR ROZA , RACHMADY WILLY , LIU MARK Y
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm-3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
摘要翻译：公开了用于形成具有高浓度硼掺杂锗的源区和漏区的晶体管器件的技术。在一些实施例中，使用选择性外延沉积在源极和漏极区域及其相应的尖端区域中提供原位硼掺杂的锗或替代地掺杂有重硼掺杂的锗层的硼掺杂硅锗。在一些这样的情况下，锗浓度可以例如超过50原子％并且高达100原子％，并且硼浓度可以例如超过1E20cm-3。提供分级锗和/或硼浓度的缓冲液可用于更好地连接不同层。在外延金属界面处掺杂在锗中的硼的浓度有效地降低了寄生电阻而不降低尖端陡峭性。该技术可以例如在平面或非平面晶体管器件中体现。

4. 发明申请

WO2011084262A3 SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS OF FABRICATION 审中-公开
标题翻译：具有垄断外来地区的半导体器件及其制造方法
公开(公告)号：WO2011084262A3
公开(公告)日：2011-09-09
申请号：PCT/US2010058199
申请日：2010-11-29
申请人： INTEL CORP , MURTHY ANAND S , AUBERTINE DANIEL BOURNE , GHANI TAHIR , PETHE ABHIJIT JAYANT
发明人： MURTHY ANAND S , AUBERTINE DANIEL BOURNE , GHANI TAHIR , PETHE ABHIJIT JAYANT
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7834 , H01L21/02057 , H01L21/02381 , H01L21/0243 , H01L21/02529 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/02636 , H01L21/28079 , H01L29/0847 , H01L29/165 , H01L29/495 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/78 , H01L29/7848 , H01L29/785 , H01L29/7853
摘要： Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.
摘要翻译：本发明的实施例描述了半导体器件上的外延区域。在一个实施例中，通过循环沉积蚀刻工艺将外延区域沉积到衬底上。在循环沉积 - 蚀刻工艺期间在间隔物下方产生的腔被外延盖层回填。外延区和外延盖层改善沟道区的电子迁移率，减少短沟道效应并降低寄生电阻。

5. 发明申请

WO2011075257A3 SPIN TORQUE MAGNETIC INTEGRATED CIRCUITS AND DEVICES THEREFOR 审中-公开
标题翻译：自旋转矩磁集成电路及其装置
公开(公告)号：WO2011075257A3
公开(公告)日：2011-09-29
申请号：PCT/US2010056735
申请日：2010-11-15
申请人： INTEL CORP , NIKONOV DMITRI E , BOURIANOFF GEORGE I , GHANI TAHIR
发明人： NIKONOV DMITRI E , BOURIANOFF GEORGE I , GHANI TAHIR
IPC分类号： G11C11/15 , G11C11/16
CPC分类号： H01L43/08 , B82Y25/00 , B82Y40/00 , G01R33/093 , G01R33/1284 , G11C11/161 , H01F10/133 , H01F10/3254 , H01F10/329 , H01F41/307 , H01L27/22 , H01L27/228 , H01L43/12
摘要： Spin torque magnetic integrated circuits and devices therefor are described. A spin torque magnetic integrated circuit includes a first free ferromagnetic layer disposed above a substrate. A non-magnetic layer is disposed above the first free ferromagnetic layer. A plurality of write pillars and a plurality of read pillars are included, each pillar disposed above the non-magnetic layer and including a fixed ferromagnetic layer.
摘要翻译：描述自旋转矩磁集成电路及其器件。自旋扭矩磁集成电路包括设置在衬底上方的第一自由铁磁层。非磁性层设置在第一自由铁磁层上方。包括多个写入柱和多个读取柱，每个柱布置在非磁性层上方并且包括固定铁磁层。

6. 发明申请

WO2011090571A3 SELF-ALIGNED CONTACTS 审中-公开
标题翻译：自我对准的联系人
公开(公告)号：WO2011090571A3
公开(公告)日：2011-11-17
申请号：PCT/US2010059302
申请日：2010-12-07
申请人： INTEL CORP , BOHR MARK T , GHANI TAHIR , RAHHAL-ORABI NADIA M , JOSHI SUBHASH , STEIGERWALD JOSEPH M , KLAUS JASON W , HWANG JACK , MACKIEWICZ RYAN
发明人： BOHR MARK T , GHANI TAHIR , RAHHAL-ORABI NADIA M , JOSHI SUBHASH , STEIGERWALD JOSEPH M , KLAUS JASON W , HWANG JACK , MACKIEWICZ RYAN
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L21/76897 , H01L21/28123 , H01L21/28229 , H01L21/28255 , H01L21/283 , H01L21/28562 , H01L21/31105 , H01L21/76802 , H01L21/76831 , H01L21/76849 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/535 , H01L29/0847 , H01L29/16 , H01L29/42364 , H01L29/456 , H01L29/495 , H01L29/4966 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/66477 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/78 , H01L29/785 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.
摘要翻译：一种晶体管，包括：衬底;衬底上的一对间隔物;衬底上以及所述一对间隔物之间的栅极电介质层;栅极电介质层上以及所述一对间隔物之间的栅极电极层; 栅电极层之间以及所述一对间隔物之间，以及与所述一对间隔物相邻的一对扩散区。绝缘盖层形成与栅极自对准的蚀刻停止结构，并防止接触蚀刻暴露栅电极，从而防止栅极与接触之间的短路。绝缘体覆盖层能够实现自对准接触，允许初始构图更宽的接触，这对于图案化限制更加稳健。

7. 发明申请

WO2012087660A2 SEMICONDUCTOR DEVICE CONTACTS 审中-公开
标题翻译：半导体器件联系人
公开(公告)号：WO2012087660A2
公开(公告)日：2012-06-28
申请号：PCT/US2011064604
申请日：2011-12-13
申请人： INTEL CORP , HAVERTY MICHAEL G , SHANKAR SADASIVAN , GHANI TAHIR , PARK SEONGJUN
发明人： HAVERTY MICHAEL G , SHANKAR SADASIVAN , GHANI TAHIR , PARK SEONGJUN
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/41791 , H01L21/283 , H01L21/3205 , H01L23/482 , H01L23/485 , H01L29/0895 , H01L29/456 , H01L29/7851 , H01L2924/0002 , H01L2924/00
摘要： Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulting layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.
摘要翻译：公开了用于在硅半导体器件中形成接触的技术。在一些实施例中，过渡层与硅半导体接触表面形成非反应性界面。在一些这种情况下，导电材料提供触点和与硅表面形成非反应性界面的材料。在其他情况下，薄的半导体或绝缘层提供与硅表面的非反应性界面并且耦合到触点的导电材料。这些技术可以例如在平面或非平面（例如，双栅极和三栅极FinFET））晶体管器件中实现。

8. 发明公开

KR20180020261A 대체 채널 FinFET들에서의 서브-핀 측벽 패시베이션 审中-公开
标题翻译：替代通道FinFET中的子引脚侧壁钝化
公开(公告)号：KR20180020261A
公开(公告)日：2018-02-27
申请号：KR20187002077
申请日：2015-06-24
申请人： INTEL CORP
发明人： GLASS GLENN A , PANG YING , MURTHY ANAND S , GHANI TAHIR , JAMBUNATHAN KARTHIK
IPC分类号： H01L21/8238 , H01L29/10 , H01L29/423 , H01L29/775 , H01L29/78
CPC分类号： H01L29/1054 , H01L21/823821 , H01L27/0924 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： 서브-핀패시베이션층의사용을통해핀-기반트랜지스터들의오프-상태누설을감소시키기위한기술들이개시된다. 일부경우들에서, 본기술들은벌크실리콘기판에희생핀들을형성하고, 얕은트렌치분리(STI) 재료를퇴적하고평탄화하는단계, 희생실리콘핀들을제거하고이를대체재료(예를들어, SiGe 또는 III-V 재료)로대체하는단계, STI 재료의적어도일부분을제거하여대체핀들의서브-핀영역들을노출시키는단계, 노출된서브-핀들에패시베이팅층/트리트먼트/시약을도포하는단계, 및추가적인 STI 재료를재퇴적하고평탄화하는단계를포함한다. 그후, 트랜지스터디바이스를완성하기위해표준트랜지스터형성공정들이수행될수 있다. 본기술들은일반적으로 STI-기반의트렌치들에서성장되는구조체들을위해임의의패시베이션층들을추가하는능력을제공한다. 패시베이션층은서브-핀소스-대-드레인(및드레인-대-소스) 전류누설을억제한다.
摘要翻译：断基于晶体管的子销针的，通过使用所述钝化层的已经用于降低公开了泄漏状态说明。在一些情况下，所述技术可消除步骤中，牺牲硅销形成在体硅衬底的牺牲销，沉积和平坦化的浅沟槽隔离（STI）的材料，而这种替换材料（例如，SiGe或III- V材料）rodae封端的步骤中，去除至少STI材料的一部分的替代销子 - 暴露针位点，施加手的暴露的子步骤当所述托架tingcheung /治疗/试剂在销，和一个额外的STI 重新沉积和平面化材料。然后可以执行标准晶体管形成工艺以完成晶体管器件。这些技术通常能够为基于STI的沟槽中生长的结构添加任意钝化层。钝化层抑制子引脚的源极至漏极（以及漏极至源极）电流泄漏。

9. 发明公开

KR20180021124A 희생 코어 상의 클래딩을 통한 트랜지스터 핀 형성 审中-公开
标题翻译：通过牺牲核心上的包层形成晶体管引脚
公开(公告)号：KR20180021124A
公开(公告)日：2018-02-28
申请号：KR20187002272
申请日：2015-06-26
申请人： INTEL CORP
发明人： GLASS GLENN A , MURTHY ANAND S , AUBERTINE DANIEL B , GHANI TAHIR , KAVALIEROS JACK T , CHU KUNG BENJAMIN , MOHAPATRA CHANDRA S , JAMBUNATHAN KARTHIK , DEWEY GILBERT , RACHMADY WILLY
IPC分类号： H01L29/78 , H01L21/84 , H01L27/12 , H01L29/06 , H01L29/66
CPC分类号： H01L29/78 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/66795
摘要： 다양한범위의채널구성및/또는재료시스템을제공하고동일한집적회로다이내에서핀-기반트랜지스터디바이스들을맞춤화하기위한기술이개시된다. 한실시예에따르면, 희생핀들이클래딩(clad)된다음, 제거됨으로써, 클래딩층을한 쌍의독립형핀들로서남겨둔다. 일단희생핀 영역들이적절한절연체로다시채워지고나면, 결과구조물은핀-온-절연체(fin-on-insulator)이다. 새로운핀들은이러한클래딩-온-코어접근법(cladding-on-core approach)을이용하여임의의재료로구성될수 있다. 결과의핀-온-절연체구조물은, 예를들어, 서브채널소스-드레인(또는드레인-소스) 누설전류를제거하거나또는달리감소시키면서양호한게이트제어를위해바람직하다. 또한, 채널-대-기판기생커패시턴스가크게감소된다. 희생핀들은코어들로간주될수 있고, 예를들어, 기판에대해네이티브재료, 또는저결함이종클래딩재료들의조합들을가능하게하는대체재료로구현될수 있다.
摘要翻译：公开了用于提供宽范围的沟道配置和/或材料系统以及在同一集成电路内定制基于管脚的晶体管器件的技术。根据一个示例，牺牲销被包覆并且然后被去除，从而使包覆层成为一对独立的销。一旦牺牲鳍区域用合适的绝缘体回填，所得到的结构就是绝缘体上的鳍。使用这种核心包层方法，新引脚可以由任何材料构成。所得到的绝缘体上销结构对于良好的栅极控制是期望的，例如，消除或以其他方式减少子沟道源极 - 漏极（或漏极 - 源极）漏电流。另外，通道 - 衬底寄生电容大大降低。牺牲翅片可以被认为是芯，并且可以用替代材料来实现，所述替代材料例如能够实现天然材料的组合，或者用于衬底的低缺陷异质包覆材料。

10. 发明公开

KR20180018506A 에피택셜적으로 성장된 소스/드레인 영역들을 갖는 트랜지스터들에서의 저항 감소 审中-公开
标题翻译：采用外延生长的源极/漏极区域的晶体管的电阻降低
公开(公告)号：KR20180018506A
公开(公告)日：2018-02-21
申请号：KR20177033116
申请日：2015-06-19
申请人： INTEL CORP
发明人： MEHANDRU RISHABH , MURTHY ANAND S , GHANI TAHIR , GLASS GLENN A , JAMBUNATHAN KARTHIK , MA SEAN T , WEBER CORY E
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/088 , H01L29/423 , H01L29/775 , H01L29/786
CPC分类号： H01L29/78 , H01L27/0886 , H01L29/42392 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78618 , H01L29/78696
摘要： 에피택셜적으로성장된붕소-도핑된실리콘게르마늄(SiGe:B) S/D 영역들을갖는 p-MOS 트랜지스터들에서의저항감소를위한기법들이개시되어있다. 이기법들은트랜지스터의실리콘(Si) 채널영역과 SiGe:B 대체 S/D 영역들사이에성장하는하나이상의계면층을포함할수 있다. 상기하나이상의계면층은다음을포함할수 있다: 붕소-도핑된 Si(Si:B)의단일층; SiGe:B의단일층 - 여기서계면층 내의 Ge 함유량은결과 SiGe:B S/D 영역들내의 Ge 함유량보다작다 -; SiGe:B의그레이딩된층(graded layer) - 여기서합금내의 Ge 함유량은낮은백분율(또는 0%)에서시작하여더 높은백분율로증가된다 -; 또는 SiGe:B의다수의계단식층 - 여기서합금내의 Ge 함유량은각각의계단에서낮은백분율(또는 0%)에서시작하여더 높은백분율로증가된다. 계면층(들)을포함시킴으로써온-상태전류흐름의저항이감소한다.
摘要翻译：硼生长外延掺杂syeoljeok硅锗：对于p-MOS晶体管eseoui电阻（硅锗B），有公开的技术与S / d的区域减小。是这样的方法是在晶体管和硅锗的硅（Si）沟道区域：可以包含生长的B之间替换S / d的区域的至少一个界面层。该至少一个界面层可以包括：硼掺杂Si（Si：B）的单层; 的SiGe：乙uidan首先 - 在所述表面层中的Ge含量为结果的SiGe：小于在B S / d区Ge含量; 的SiGe：在合金中的B-Ge含量的梯度层（倾斜层）增加，其中较高的百分比，开始在低百分比（或0％）; 或SiGe：多个所述B的级联层 - 其中在合金的Ge含量通过在开始在各个步骤中低百分比（或0％）增加至更高的百分比。通过包括界面层，导通电流的电阻减小。

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