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1. 发明申请

WO2012087581A3 TRANSISTORS WITH HIGH CONCENTRATION OF BORON DOPED GERMANIUM 审中-公开
标题翻译：高浓度硼掺杂锗的晶体管
公开(公告)号：WO2012087581A3
公开(公告)日：2012-09-07
申请号：PCT/US2011063813
申请日：2011-12-07
申请人： INTEL CORP , MURTHY ANAND S , GLASS GLENN A , GHANI TAHIR , PILLARISETTY RAVI , MUKHERJEE NILOY , KAVALIEROS JACK T , KOTLYAR ROZA , RACHMADY WILLY , LIU MARK Y
发明人： MURTHY ANAND S , GLASS GLENN A , GHANI TAHIR , PILLARISETTY RAVI , MUKHERJEE NILOY , KAVALIEROS JACK T , KOTLYAR ROZA , RACHMADY WILLY , LIU MARK Y
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm-3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
摘要翻译：公开了用于形成具有高浓度硼掺杂锗的源区和漏区的晶体管器件的技术。在一些实施例中，使用选择性外延沉积在源极和漏极区域及其相应的尖端区域中提供原位硼掺杂的锗或替代地掺杂有重硼掺杂的锗层的硼掺杂硅锗。在一些这样的情况下，锗浓度可以例如超过50原子％并且高达100原子％，并且硼浓度可以例如超过1E20cm-3。提供分级锗和/或硼浓度的缓冲液可用于更好地连接不同层。在外延金属界面处掺杂在锗中的硼的浓度有效地降低了寄生电阻而不降低尖端陡峭性。该技术可以例如在平面或非平面晶体管器件中体现。

2. 发明申请

WO2011090583A3 GERMANIUM-BASED QUANTUM WELL DEVICES 审中-公开
标题翻译：基于锗的量子阱器件
公开(公告)号：WO2011090583A3
公开(公告)日：2011-10-13
申请号：PCT/US2010059620
申请日：2010-12-09
申请人： INTEL CORP , PILLARISETTY RAVI , JIN BEEN-YIH , CHU-KUNG BENJAMIN , METZ MATTHEW V , KAVALIEROS JACK T , RADOSAVLJEVIC MARKO , KOTLYAR ROZA , RACHMADY WILLY , MUKHERJEE NILOY , DEWEY GILBERT , CHAU ROBERT
发明人： PILLARISETTY RAVI , JIN BEEN-YIH , CHU-KUNG BENJAMIN , METZ MATTHEW V , KAVALIEROS JACK T , RADOSAVLJEVIC MARKO , KOTLYAR ROZA , RACHMADY WILLY , MUKHERJEE NILOY , DEWEY GILBERT , CHAU ROBERT
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
摘要翻译：量子阱晶体管具有锗量子阱沟道区域。含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。通道区域上方和下方的分级硅锗层提高性能。多栅极电介质材料允许使用高k值栅极电介质。

3. 发明专利

SG11201601319QA GE AND III-V CHANNEL SEMICONDUCTOR DEVICES HAVING MAXIMIZED COMPLIANCE AND FREE SURFACE RELAXATION 未知
公开(公告)号：SG11201601319QA
公开(公告)日：2016-03-30
申请号：SG11201601319Q
申请日：2013-09-27
申请人： INTEL CORP , PILLARISETTY RAVI , DASGUPTA SANSAPTAK , GOEL NITI , LE VAN H , RADOSAVLJEVIC MARKO , DEWEY GILBERT , MUKHERJEE NILOY , METZ MATTHEW V , RACHMADY WILLY , KAVALIEROS JACK T , CHU-KUNG BENJAMIN , KENNEL HAROLD W , CEA STEPHEN M , CHAU ROBERT S
发明人： PILLARISETTY RAVI , DASGUPTA SANSAPTAK , GOEL NITI , LE VAN H , RADOSAVLJEVIC MARKO , DEWEY GILBERT , MUKHERJEE NILOY , METZ MATTHEW V , RACHMADY WILLY , KAVALIEROS JACK T , CHU-KUNG BENJAMIN , KENNEL HAROLD W , CEA STEPHEN M , CHAU ROBERT S
IPC分类号： H01L21/336 , H01L29/78
摘要： Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

4. 发明申请

WO2011087606A3 TECHNIQUES FOR FORMING CONTACTS TO QUANTUM WELL TRANSISTORS 审中-公开
标题翻译：形成与量子阱晶体管接触的技术
公开(公告)号：WO2011087606A3
公开(公告)日：2011-10-20
申请号：PCT/US2010058683
申请日：2010-12-02
申请人： INTEL CORP , PILLARISETTY RAVI , KAVALIEROS JACK T , CHU-KUNG BENJAMIN , RACHMADY WILLY , HUDAIT MANTU K , MUKHERJEE NILOY , RADOSAVLJEVIC MARKO , CHAU ROBERT S
发明人： PILLARISETTY RAVI , KAVALIEROS JACK T , CHU-KUNG BENJAMIN , RACHMADY WILLY , HUDAIT MANTU K , MUKHERJEE NILOY , RADOSAVLJEVIC MARKO , CHAU ROBERT S
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： H01L29/7784 , H01L29/151 , H01L29/155 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41775 , H01L29/42316 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/775 , H01L29/7783 , H01L29/78
摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
摘要翻译：公开了用于向在半导体异质结构中形成的器件提供低电阻自对准接触的技术。例如，该技术可用于形成在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。与导致源极/漏极触点与栅极之间的相对较大空间的常规接触工艺流程不同，由本文描述的技术提供的所得源极触点和漏极触点是自对准的，因为每个触点与栅极电极对齐并且被隔离由此通过间隔材料。

5. 发明申请

WO2012040075A3 NON-PLANAR DEVICE HAVING UNIAXIALLY STRAINED FIN AND METHOD OF MAKING SAME 审中-公开
标题翻译：具有非均匀应变FIN的非平面设备及其制造方法
公开(公告)号：WO2012040075A3
公开(公告)日：2012-06-07
申请号：PCT/US2011052084
申请日：2011-09-19
申请人： INTEL CORP , CEA STEPHEN M , KOTLYAR ROZA , KAVALIEROS JACK T , GILES MARTIN D , GHANI TAHIR , KUHN KELIN J , KUHN MARKUS , ZELICK NANCY M
发明人： CEA STEPHEN M , KOTLYAR ROZA , KAVALIEROS JACK T , GILES MARTIN D , GHANI TAHIR , KUHN KELIN J , KUHN MARKUS , ZELICK NANCY M
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/1054 , H01L29/66795 , H01L29/7849 , H01L29/785
摘要： A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.
摘要翻译：根据该方法制造的方法和装置。该方法包括提供包括第一材料的基底，并且提供包括第二材料的翅片，所述翅片设置在所述基底上并且具有器件活性部分，所述第一材料和所述第二材料在其各自的结晶结构之间呈现晶格失配。提供散热片包括在基板上提供包括第二材料的双轴应变膜; 并除去双轴应变膜的部分以形成基本上单轴应变的翅片。

6. 发明申请

WO2011087610A3 CONDUCTIVITY IMPROVEMENTS FOR III-V SEMICONDUCTOR DEVICES 审中-公开
标题翻译： III-V族半导体器件的电导率改进
公开(公告)号：WO2011087610A3
公开(公告)日：2011-10-20
申请号：PCT/US2010058784
申请日：2010-12-02
申请人： INTEL CORP , KAVALIEROS JACK T , RACHMADY WILLY , MUKHERJEE NILOY , RADOSAVLJEVIC MARKO , GOE NITI , LEE YONG JU , MAJHI PRASHANT , TSAI WILMAN , DEWEY GILBERT
发明人： KAVALIEROS JACK T , RACHMADY WILLY , MUKHERJEE NILOY , RADOSAVLJEVIC MARKO , GOE NITI , LEE YONG JU , MAJHI PRASHANT , TSAI WILMAN , DEWEY GILBERT
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/7786 , H01L21/2256 , H01L29/20 , H01L29/42316 , H01L29/47 , H01L29/66431 , H01L29/66462 , H01L29/7787
摘要： Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.
摘要翻译：描述了III-V半导体器件的导电性改进。第一种改进包括与沟道层不共面的平面的阻挡层。第二个改进包括金属/ Si，Ge或硅锗/ III-V堆叠的退火以在Si和/或锗掺杂的III-V层上形成金属硅，金属锗或金属硅锗层。然后，去除金属层并在金属硅，金属锗或金属硅锗层上形成源极/漏极。第三种改进包括在III-V沟道层上形成IV族和/或VI族元素层，并退火以III-V族沟道层掺杂IV族和/或VI族物质。第四种改进包括形成在III-V器件的接入区域上方的钝化层和/或偶极子层。

7. 发明申请

WO2010078051A3 EMBEDDED MEMORY CELL AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译：嵌入式存储器单元及其制造方法
公开(公告)号：WO2010078051A3
公开(公告)日：2010-09-02
申请号：PCT/US2009068524
申请日：2009-12-17
申请人： INTEL CORP , KAVALIEROS JACK T , MUKHERJEE NILOY , DEWEY GILBERT , SOMASEKHAR DINESH , DOYLE BRIAN S
发明人： KAVALIEROS JACK T , MUKHERJEE NILOY , DEWEY GILBERT , SOMASEKHAR DINESH , DOYLE BRIAN S
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L29/66181 , H01L27/10832 , H01L27/10861 , H01L27/10867 , H01L27/1087 , H01L27/10876 , H01L28/90 , H01L29/66666 , H01L29/7827
摘要： An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the semiconducting substrate, and a capacitor (130) at least partially embedded in the semiconducting substrate. The capacitor includes a first electrode (131) and a second electrode (132) that are electrically isolated from each other by a first electrically insulating material (133). The first electrode is electrically connected to the semiconducting substrate and the second electrode is electrically connected to the source/drain region of the transistor.
摘要翻译：嵌入式存储单元包括半导体衬底（110），具有至少部分嵌入半导体衬底中的源极/漏极区域（121）的晶体管（120）以及至少部分嵌入半导体衬底中的电容器（130）。电容器包括通过第一电绝缘材料（133）彼此电隔离的第一电极（131）和第二电极（132）。第一电极电连接到半导体衬底并且第二电极电连接到晶体管的源极/漏极区域。

8. 发明申请

WO2008094287A3 THREE-DIMENSIONAL INTEGRATED CIRCUIT FOR ANALYTE DETECTION 审中-公开
标题翻译：用于分析检测的三维集成电路
公开(公告)号：WO2008094287A3
公开(公告)日：2008-12-04
申请号：PCT/US2007072424
申请日：2007-06-28
申请人： INTEL CORP , DATTA SUMAN , RAMANATHAN SHRIRAM , KAVALIEROS JACK T , BRASK JUSTIN K , BARNETT BRANDON
发明人： DATTA SUMAN , RAMANATHAN SHRIRAM , KAVALIEROS JACK T , BRASK JUSTIN K , BARNETT BRANDON
IPC分类号： H01L21/20 , H01L21/336
CPC分类号： G01N27/4145 , G01N27/4146 , Y10T436/143333
摘要： The embodiments of the invention relate to a device having a first substrate comprising a transistor; a second substrate; an insulating layer in between and adjoining the first and second substrates; and an opening within the second substrate, the opening being aligned with the transistor; wherein the transistor is configured to detect an electrical charge change within the opening. Other embodiments relate to a method including providing a substrate comprising a first part, a second part, and an insulating layer in between and adjoining the first and second parts; fabricating a transistor on the first part; and fabricating an opening within the second part, the opening being aligned with the transistor; wherein the transistor is configured to detect an electrical charge change within the opening.
摘要翻译：本发明的实施例涉及具有包括晶体管的第一衬底的器件; 第二基板; 位于第一和第二基板之间并邻接第一和第二基板的绝缘层; 以及在所述第二基板内的开口，所述开口与所述晶体管对准; 其中所述晶体管被配置为检测所述开口内的电荷变化。其他实施例涉及一种方法，包括提供包括第一部分，第二部分和绝缘层的基板，并且邻近第一和第二部分; 在第一部分制造晶体管; 以及在所述第二部分内制造开口，所述开口与所述晶体管对准; 其中所述晶体管被配置为检测所述开口内的电荷变化。

9. 发明申请

WO2009032581A2 HIGH HOLE MOBILITY P-CHANNEL GE TRANSISTOR STRUCTURE ON SI SUBSTRATE 审中-公开
标题翻译： SI基板上的高霍尔移动性P沟道GE晶体管结构
公开(公告)号：WO2009032581A2
公开(公告)日：2009-03-12
申请号：PCT/US2008074173
申请日：2008-08-25
申请人： INTEL CORP , HUDAIT MANTU K , DATTA SUMAN , KAVALIEROS JACK T , TOLCHINSKY PETER G
发明人： HUDAIT MANTU K , DATTA SUMAN , KAVALIEROS JACK T , TOLCHINSKY PETER G
IPC分类号： H01L29/772 , H01L29/78
CPC分类号： H01L29/7782 , H01L21/02381 , H01L21/02433 , H01L21/02463 , H01L21/02505 , H01L21/02546 , H01L21/02573 , H01L21/0262 , H01L29/267 , H01L29/66431
摘要： The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium ("Ge") transistor structure on a Silicon ("Si") substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了用于在硅（“Si”）衬底上实现高空穴迁移率p沟道锗（“Ge”）晶体管结构的装置和方法。一个示例性装置可以包括包含GaAs成核层，第一GaAs缓冲层和第二GaAs缓冲层的缓冲层。示例性装置可以进一步包括在第二GaAs缓冲层上的底部势垒，其具有大于1.1eV的带隙，底部势垒上的Ge有源沟道层并且相对于底部势垒具有大于0.3的价带偏移 eV，以及Ge有源沟道层上的AlAs顶部势垒，其中AlAs顶部势垒具有大于1.1eV的带隙。当然，在不脱离本实施例的情况下，可以有许多替换，变化和修改。

10. 发明申请

WO2009012053A3 ISOLATED TRI-GATE TRANSISTOR FABRICATED ON BULK SUBSTRATE 审中-公开
标题翻译：散装基板上制造的隔离式三栅极晶体管
公开(公告)号：WO2009012053A3
公开(公告)日：2009-03-12
申请号：PCT/US2008068855
申请日：2008-06-30
申请人： INTEL CORP , RIOS RAFAEL , KAVALIEROS JACK T , CEA STEPHEN M
发明人： RIOS RAFAEL , KAVALIEROS JACK T , CEA STEPHEN M
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900°C and around 1100°C for a time duration between around 0.5 hours and around 3 hours.
摘要翻译：一种形成隔离的三栅极半导体主体的方法包括：图案化体衬底以形成鳍状结构;在鳍状结构周围沉积绝缘材料;使绝缘材料凹陷以暴露将用于三端口的鳍状结构的一部分在所述鳍结构的暴露部分上沉积氮化物帽以保护所述鳍结构的暴露部分，并且执行热氧化工艺以氧化所述氮化物帽下方的所述鳍结构的未受保护部分。鳍状物的氧化部分隔离被氮化物帽保护的半导体主体。然后可以去除氮化物帽。热氧化工艺可以包括在约900℃和约1100℃之间的温度下退火衬底约0.5小时至约3小时之间的持续时间。

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