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1. 发明申请

WO2009042981A2 METHOD TO INTRODUCE UNIAXIAL STRAIN IN MULTIGATE NANOSCALE TRANSISTORS BY SELF ALIGNED SI TO SIGE CONVERSION PROCESSES AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：在多重纳米级晶体管中引入自对准SI到SIGE转换过程的单轴应变及其结构的方法
公开(公告)号：WO2009042981A2
公开(公告)日：2009-04-02
申请号：PCT/US2008/078041
申请日：2008-09-28
申请人： INTEL CORPORATION , JIN, Been-yih , DOYLE, Brian , KAVALIEROS, Jack , DATTA, Suman
发明人： JIN, Been-yih , DOYLE, Brian , KAVALIEROS, Jack , DATTA, Suman
IPC分类号： H01L29/78 , H01L29/80
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7848
摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods may include providing a gate electrode comprising a top surface and first and second laterally opposite sidewalls, wherein a hard mask is disposed on the top surface, a source drain region disposed on opposite sides of the gate electrode, and a spacer disposed on the first and second laterally opposed sidewalls of the gate electrode, forming a silicon germanium layer on exposed portions of the top surface and the first and second laterally opposite sidewalls of the source drain region and then oxidizing a portion of the silicon germanium layer, wherein a germanium portion of the silicon germanium layer is forced down into the source drain region to convert a silicon portion of the source drain region into a silicon germanium portion of the source drain region.
摘要翻译：描述了形成微电子结构的方法。这些方法的实施例可以包括提供包括顶表面以及第一和第二横向相对侧壁的栅电极，其中硬掩模设置在顶表面上，设置在栅电极的相对侧上的源极漏极区和设置的间隔件在栅电极的第一和第二横向相对侧壁上，在源极漏极区的顶表面和第一和第二横向相对侧壁的暴露部分上形成硅锗层，然后氧化硅锗层的一部分，其中硅锗层的锗部分被向下压入源极漏极区域，以将源极漏极区域的硅部分转换成源极漏极区域的硅锗部分。

2. 发明申请

WO2009088587A2 METHODS OF FORMING NANODOTS USING SPACER PATTERNING TECHNIQUES AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：使用间隔物图案化技术形成纳米点的方法和由其形成的结构
公开(公告)号：WO2009088587A2
公开(公告)日：2009-07-16
申请号：PCT/US2008/085226
申请日：2008-12-02
申请人： INTEL CORPORATION , DOYLE, Brian , JIN, Been-Yih , KAVALIEROS, Jack , CHAU, Robert
发明人： DOYLE, Brian , JIN, Been-Yih , KAVALIEROS, Jack , CHAU, Robert
IPC分类号： H01L21/027 , B82B3/00
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , Y10T428/24612
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a first block on a nanodot material, forming a first spacer on the first block, removing the first block to form a free standing spacer, removing exposed portions of the nanodot material and then the free standing spacer to form nanowires, forming a second block at an angle to a length of the nanowires, forming a second spacer on the second block, forming a second free standing spacer on the nanowires by removing the second block, and removing exposed portions of the nanowires and then the second free standing spacer to form an ordered array of nanodots.
摘要翻译：描述了形成微电子器件的方法和相关结构。那些方法可包括在纳米点材料上形成第一块，在第一块上形成第一间隔物，除去第一块以形成独立式间隔物，除去纳米点材料的暴露部分，然后去除独立式间隔物以形成纳米线，以与纳米线的长度成一定角度形成第二块，在第二块上形成第二间隔物，通过除去第二块在纳米线上形成第二独立式间隔物，以及除去纳米线的暴露部分，然后除去第二游离物站立隔离器形成一个有序的纳米点阵列。

3. 发明申请

WO2009032576A3 METHOD TO FABRICATE ADJACENT SILICON FINS OF DIFFERING HEIGHTS 审中-公开
标题翻译：制造不同高度的相邻硅片的方法
公开(公告)号：WO2009032576A3
公开(公告)日：2009-05-07
申请号：PCT/US2008074161
申请日：2008-08-25
申请人： INTEL CORP , DOYLE BRIAN S , JIN BEEN-YIH , SHAH UDAY
发明人： DOYLE BRIAN S , JIN BEEN-YIH , SHAH UDAY
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L29/785 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L29/66795
摘要： A method to fabricate adjacent silicon fins of differing heights comprises providing a silicon substrate having an isolation layer deposited thereon, patterning the isolation layer to form first and second isolation structures, patterning the silicon substrate to form a first silicon fin beneath the first isolation structure and a second silicon fin beneath the second isolation structure, depositing an insulating layer on the substrate, planarizing the insulating layer to expose top surfaces of the first and second isolation structures, depositing and patterning a masking layer to mask the first isolation structure but not the second isolation structure, applying a wet etch to remove the second isolation structure and expose the second silicon fin, epitaxially depositing a silicon layer on the second silicon fin, and recessing the insulating layer to expose at least a portion of the first silicon fin and at least a portion of the second silicon fin.
摘要翻译：制造具有不同高度的相邻硅鳍的方法包括：提供其上沉积有隔离层的硅衬底;图案化隔离层以形成第一和第二隔离结构;图案化硅衬底以在第一隔离结构下形成第一硅鳍;以及在所述第二隔离结构下方的第二硅鳍状物，在所述衬底上沉积绝缘层，平坦化所述绝缘层以暴露所述第一和第二隔离结构的顶表面，沉积并图案化掩模层以掩蔽所述第一隔离结构而不是所述第二施加湿蚀刻以去除第二隔离结构并暴露第二硅鳍;在第二硅鳍上外延沉积硅层;以及使绝缘层凹陷以暴露第一硅鳍的至少一部分，并且至少第二硅鳍的一部分。

4. 发明申请

WO2007078892A3 A TENSILE STRAINED NMOS TRANSISTOR USING GROUP III-N SOURCE/DRAIN REGIONS 审中-公开
公开(公告)号：WO2007078892A3
公开(公告)日：2007-07-12
申请号：PCT/US2006/048078
申请日：2006-12-15
申请人： INTEL CORPORATION , DATTA, Suman , BRASK, Justin, K. , JIN, Been-yih , KAVALIEROS, Jack, T. , HUDAIT, Mantu, K.
发明人： DATTA, Suman , BRASK, Justin, K. , JIN, Been-yih , KAVALIEROS, Jack, T. , HUDAIT, Mantu, K.
IPC分类号： H01L21/336 , H01L29/10
摘要： Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.

5. 发明申请

WO2006078469A1 NON-PLANAR MOS STRUCTURE WITH A STRAINED CHANNEL REGION 审中-公开
标题翻译：具有应变通道区域的非平面MOS结构
公开(公告)号：WO2006078469A1
公开(公告)日：2006-07-27
申请号：PCT/US2006/000378
申请日：2006-01-04
申请人： INTEL CORPORATION , DOYLE, Brian , DATTA, Suman , JIN, Been-Yih , CHAU, Robert
发明人： DOYLE, Brian , DATTA, Suman , JIN, Been-Yih , CHAU, Robert
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78687
摘要： An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate length width versus a non-planar MOS structure with an unstrained channel or planar MOS structure including a strained channel.
摘要翻译：一个实施例是包括应变通道区域的非平面MOS晶体管结构。具有应变通道优点的非平面MOS晶体管结构，特别是NMOS三栅极晶体管的组合产生了对于给定栅极长度宽度相对于非晶体管的晶体管驱动电流，开关速度和降低的漏电流具有包含应变通道的无约束通道或平面MOS结构的平面MOS结构。

6. 发明申请

WO2005067055A1 TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER 审中-公开
标题翻译：具有导体材料层的晶体管栅极电极
公开(公告)号：WO2005067055A1
公开(公告)日：2005-07-21
申请号：PCT/US2004/043663
申请日：2004-12-22
申请人： INTEL CORPORATION , MURPHY, Anand , BOYANOV, Boyan , DATTA, Suman , DOYLE, Brian, S. , JIN, Been-Yih , YU, Shaofeng , CHAU, Robert
发明人： MURPHY, Anand , BOYANOV, Boyan , DATTA, Suman , DOYLE, Brian, S. , JIN, Been-Yih , YU, Shaofeng , CHAU, Robert
IPC分类号： H01L29/10
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： Various embodiments of the invention relates to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
摘要翻译：本发明的各种实施例涉及一种在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有工作功能的栅电极导体材料在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

7. 发明申请

WO1996014164A1 SPIN-ON-GLASS PROCESS WITH CONTROLLED ENVIRONMENT 审中-公开
标题翻译：带控制环境的旋转玻璃工艺
公开(公告)号：WO1996014164A1
公开(公告)日：1996-05-17
申请号：PCT/US1994012785
申请日：1994-11-07
申请人： MACRONIX INTERNATIONAL CO., LTD. , YEN, Daniel, L., W. , JIN, Been, Yih , WANG, Ming, Hong
发明人： MACRONIX INTERNATIONAL CO., LTD.
IPC分类号： B05D03/12
CPC分类号： B05C11/08 , B05D1/005 , H01L21/314
摘要： A process for spreading and flowing in a flowable dielectric (25) during manufacture of an integrated circuit resulting in greater planarity and better gap filling ability. The process involves spinning the integrated circuit while controlling evaporation of the solvent from the flowable dielectric (25) to increase the amount of flow in time and decrease spin velocity during flow in to improve planarity in gap filling ability. The process includes supporting the integrated circuit in a chamber; dispensing the flowable dielectric (25) in a solvent on the integrated circuit in the chamber; covering the integrated circuit to provide a controllable environment within the chamber after the step of dispensing; spinning the integrated circuit while controlling the controllable environment to spread and flow in the flowable dielectric (25); uncovering the integrated circuit within the chamber; spinning the integrated circuit to spin off flowable dielectric (25); and curing the flowable dielectric (25).
摘要翻译：在集成电路的制造期间在可流动电介质（25）中扩展和流动的过程，导致更大的平坦度和更好的间隙填充能力。该方法包括旋转集成电路，同时控制来自可流动介质（25）的溶剂的蒸发，以增加流动量，并减少流动期间的旋转速度，以提高间隙填充能力的平面度。该过程包括将集成电路支撑在腔室中; 将所述可流动介质（25）分配在所述腔室中的集成电路上的溶剂中; 覆盖集成电路以在分配步骤之后在腔室内提供可控的环境; 旋转集成电路，同时控制可控环境以在可流动介质（25）中扩散和流动; 露出腔室内的集成电路; 旋转集成电路以分离可流动电介质（25）; 并固化可流动电介质（25）。

8. 发明申请

WO2011075228A2 ISOLATION FOR NANOWIRE DEVICES 审中-公开
标题翻译：纳米器件的隔离
公开(公告)号：WO2011075228A2
公开(公告)日：2011-06-23
申请号：PCT/US2010055225
申请日：2010-11-03
申请人： INTEL CORP , SHAH UDAY , CHU-KUNG BENJAMIN , JIN BEEN-YIH , PILLARISETTY RAVI , RADOSAVLJEVIC MARKO , RACHMADY WILLY
发明人： SHAH UDAY , CHU-KUNG BENJAMIN , JIN BEEN-YIH , PILLARISETTY RAVI , RADOSAVLJEVIC MARKO , RACHMADY WILLY
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/02236 , H01L21/02532 , H01L21/02603 , H01L21/76224 , H01L29/0649 , H01L29/0653 , H01L29/0669 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/78 , H01L29/78696 , H01L2221/1094
摘要： The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.
摘要翻译：本公开涉及制造微电子器件的领域。在至少一个实施方案中，本公开涉及形成分离的纳米线，其中与纳米线相邻的隔离结构为其上形成微电子结构提供基本上水平的表面。

9. 发明申请

WO2010107571A2 APPARATUS AND METHODS FOR IMPROVING PARALLEL CONDUCTION IN A QUANTUM WELL DEVICE 审中-公开
标题翻译：用于改善量子阱器件中并联导通的装置和方法
公开(公告)号：WO2010107571A2
公开(公告)日：2010-09-23
申请号：PCT/US2010/025845
申请日：2010-03-02
申请人： INTEL CORPORATION , PILLARISETTY, Ravi , HUDAIT, Mantu , JIN, Been-Yih , CHU-KUNG, Benjamin , CHAU, Robert
发明人： PILLARISETTY, Ravi , HUDAIT, Mantu , JIN, Been-Yih , CHU-KUNG, Benjamin , CHAU, Robert
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66977 , H01L29/1083 , H01L29/161 , H01L29/365 , H01L29/66431 , H01L29/66439 , H01L29/7781
摘要： Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
摘要翻译：本文通常描述了提供用于改进的并联传导的量子阱装置的装置和方法的实施例。可以描述和要求保护其他实施例。

10. 发明申请

WO2009042981A3 METHOD TO INTRODUCE UNIAXIAL STRAIN IN MULTIGATE NANOSCALE TRANSISTORS BY SELF ALIGNED SI TO SIGE CONVERSION PROCESSES AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：通过自对准SI引入多元纳米晶体管中的单轴应变的方法来标识形成的转换过程和结构
公开(公告)号：WO2009042981A3
公开(公告)日：2009-06-04
申请号：PCT/US2008078041
申请日：2008-09-28
申请人： INTEL CORP , JIN BEEN-YIH , DOYLE BRIAN , KAVALIEROS JACK , DATTA SUMAN
发明人： JIN BEEN-YIH , DOYLE BRIAN , KAVALIEROS JACK , DATTA SUMAN
IPC分类号： H01L29/78 , H01L29/00 , H01L29/80
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7848
摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods may include providing a gate electrode comprising a top surface and first and second laterally opposite sidewalls, wherein a hard mask is disposed on the top surface, a source drain region disposed on opposite sides of the gate electrode, and a spacer disposed on the first and second laterally opposed sidewalls of the gate electrode, forming a silicon germanium layer on exposed portions of the top surface and the first and second laterally opposite sidewalls of the source drain region and then oxidizing a portion of the silicon germanium layer, wherein a germanium portion of the silicon germanium layer is forced down into the source drain region to convert a silicon portion of the source drain region into a silicon germanium portion of the source drain region.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例可以包括提供包括顶表面和第一和第二横向相对的侧壁的栅电极，其中硬掩模设置在顶表面上，源极漏极区域设置在栅电极的相对侧上，在栅电极的第一和第二横向相对的侧壁上，在源漏区的顶表面和第一和第二横向相对的侧壁的暴露部分上形成硅锗层，然后氧化硅锗层的一部分，其中硅锗层的锗部分被迫下降到源极漏极区域中，以将源极区域的硅部分转换成源极漏极区域的硅锗部分。

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