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1. 发明申请

WO2012087548A3 VECTOR CONFLICT INSTRUCTIONS 审中-公开
标题翻译：矢量冲突指示
公开(公告)号：WO2012087548A3
公开(公告)日：2012-08-16
申请号：PCT/US2011063307
申请日：2011-12-05
申请人： INTEL CORP , HUGHES CHRISTOPHER J , CHARNEY MARK J , CHEN YEN-KUANG , CORBAL JESUS , FORSYTH ANDREW T , GIRKAR MILIND B , HALL JONATHAN C , IDO HIDEKI , VALENTINE ROBERT , WIEDEMEIER JEFFREY
发明人： HUGHES CHRISTOPHER J , CHARNEY MARK J , CHEN YEN-KUANG , CORBAL JESUS , FORSYTH ANDREW T , GIRKAR MILIND B , HALL JONATHAN C , IDO HIDEKI , VALENTINE ROBERT , WIEDEMEIER JEFFREY
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30043 , G06F9/3838
摘要： A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.
摘要翻译：描述了在半导体芯片上实现的处理核心，其具有包括第一比较电路的第一执行单元逻辑电路，以将第一输入向量中的每个元素与第二输入向量的每个元素进行比较。处理核心还具有第二执行逻辑电路，其包括第二比较电路，用于将第一输入值与输入向量的每个数据元素进行比较。

2. 发明申请

WO2012087583A3 MECHANISM FOR CONFLICT DETECTION USING SIMD 审中-公开
标题翻译：使用SIMD进行冲突检测的机制
公开(公告)号：WO2012087583A3
公开(公告)日：2012-09-27
申请号：PCT/US2011063836
申请日：2011-12-07
申请人： INTEL CORP , SMELYANSKIY MIKHAIL , CHEN YEN-KUANG , KIM DAEHYUN , HUGHES CHRISTOPHER J , LEE VICTOR W
发明人： SMELYANSKIY MIKHAIL , CHEN YEN-KUANG , KIM DAEHYUN , HUGHES CHRISTOPHER J , LEE VICTOR W
IPC分类号： G06F13/16 , G06F15/80
CPC分类号： G06F9/3887 , G06F9/345
摘要： A system and method are configured to detect conflicts when converting scalar processes to parallel processes ("SIMDifying"). Conflicts may be detected for an unordered single index, an ordered single index and/or ordered pairs of indices. Conflicts may be further detected for read-after-write dependencies. Conflict detection is configured to identify operations (i.e., iterations) in a sequence of iterations that may not be done in parallel.
摘要翻译：将系统和方法配置为在将标量过程转换为并行进程（“SIMDifying”）时检测冲突。可以针对无序单索引，有序单索引和/或有序索引对检测冲突。读写依赖关系可能会进一步检测到冲突。冲突检测被配置为识别可能不并行完成的迭代序列中的操作（即迭代）。

3. 发明专利

JP2011123494A Method and system to traverse graph-based network 审中-公开
标题翻译：用于基于图形的网络的方法和系统
公开(公告)号：JP2011123494A
公开(公告)日：2011-06-23
申请号：JP2010276067
申请日：2010-12-10
申请人： Intel Corp , インテルコーポレイション
发明人： YOU KISUN , HUGHES CHRISTOPHER J , CHEN YEAN-KUANG
IPC分类号： G10L15/18 , G10L15/28
CPC分类号： G10L15/063 , G10L15/02 , G10L15/083 , G10L15/19 , G10L15/34
摘要： PROBLEM TO BE SOLVED: To provide methods and systems to translate input labels of arcs of a network, corresponding to a sequence of states of the network, to a list of output grammar elements of the arcs, corresponding to a sequence of grammar elements.
SOLUTION: The network may include a plurality of speech recognition models combined with a weighted finite state transducer (WFST). Traversal may include active arc traversal, and may include active arc propagation. Arcs may be processed in parallel, including arcs originating from multiple source states and directed to a common destination state. Self-loops associated with states may be modeled within outgoing arcs of the states, which may reduce synchronization operations. Tasks may be ordered with respect to cache-data locality to associate tasks with processing threads based on at least part on whether another task associated with a corresponding data object was previously assigned to the thread.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供方法和系统，将对应于网络状态序列的网络的弧的输入标签转换成对应于语法序列的弧的输出语法元素的列表元素。解决方案：网络可以包括与加权有限状态换能器（WFST）组合的多个语音识别模型。穿越可能包括有效的电弧遍历，并且可能包括有效的电弧传播。弧可以并行处理，包括源自多个源状态并被引导到公共目的地状态的弧。与状态相关联的自环可以在状态的输出弧内被建模，这可以减少同步操作。至少部分地基于与相应的数据对象相关联的另一任务是否先前已经被分配给线程，可以针对高速缓存数据本地来命令任务来将任务与处理线程相关联。版权所有（C）2011，JPO＆INPIT

4. 发明公开

EP2656229A4 MECHANISM FOR CONFLICT DETECTION USING SIMD 审中-公开
公开(公告)号：EP2656229A4
公开(公告)日：2018-04-04
申请号：EP11851547
申请日：2011-12-07
申请人： INTEL CORP
发明人： SMELYANSKIY MIKHAIL , CHEN YEN KUANG , KIM DAEHYUN , HUGHES CHRISTOPHER J , LEE VICTOR W
IPC分类号： G06F13/16 , G06F9/30 , G06F9/345 , G06F15/80
CPC分类号： G06F9/3887 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/345
摘要： A system and method are configured to detect conflicts when converting scalar processes to parallel processes (“SIMDifying”). Conflicts may be detected for an unordered single index, an ordered single index and/or ordered pairs of indices. Conflicts may be further detected for read-after-write dependencies. Conflict detection is configured to identify operations (i.e., iterations) in a sequence of iterations that may not be done in parallel.

5. 发明专利

GB2518116A Vector move instruction controlled by read and write masks 未知
公开(公告)号：GB2518116A
公开(公告)日：2015-03-11
申请号：GB201500819
申请日：2013-06-12
申请人： INTEL CORP
发明人： PLOTNIKOV MIKHAIL , NARAIKIN ANDREY , HUGHES CHRISTOPHER J
IPC分类号： G06F15/80 , G06F9/38
摘要： A processor executes a vector move instruction to move data elements from a second vector register to a first vector register under the control of a first mask register and a second mask register. A register file within the processor includes the first vector register, the second vector register, the first mask register and the second mask register. In response to the vector move instruction, execution circuitry in the processor is to replace a given number of target data elements in the first vector register with the given number of source data elements in the second vector register. Each source data element corresponds to a mask bit in the second mask register having a second bit value, and wherein each target data element corresponds to a mask bit in the first mask register having a first bit value.

6. 发明专利

GB2503169A Systems, apparatuses, and methods for stride pattern gathering of data elements and stride pattern scattering of data elements 未知
公开(公告)号：GB2503169A
公开(公告)日：2013-12-18
申请号：GB201316951
申请日：2011-12-06
申请人： INTEL CORP
发明人： VALENTINE ROBERT C , HUGHES CHRISTOPHER J , ADRIAN JESUS CORBAL SAN , SANS ROGER ESPASA , TOLL BRET L , GIRKAR MILIND BABURAO , FORSYTH ANDREW THOMAS , GROCHOWSKI EDWARD THOMAS , HALL JONATHAN CANNON
IPC分类号： G06F9/30
摘要： Embodiments of systems, apparatuses, and methods for performing gather and scatter stride instruction in a computer processor are described. In some embodiments, the execution of a gather stride instruction causes a conditionally storage of strided data elements from memory into the destination register according to at least some of bit values of a writemask

8. 发明专利

DE112016004348T5 STREUEN-DURCH-INDIZES-ZU-REGISTER- UND DATENELEMENTUMORDNUNGSPROZESSOREN, -VERFAHREN, -SYSTEME UND -BEFEHLE 未知
公开(公告)号：DE112016004348T5
公开(公告)日：2018-06-21
申请号：DE112016004348
申请日：2016-08-08
申请人： INTEL CORP
发明人： HUGHES CHRISTOPHER J , PARK JONG SOO
IPC分类号： G06F9/30 , G06F9/38
摘要： Ein Prozessor enthält eine Decodiereinheit, um einen Befehl zu decodieren, der einen gepackten Quelldatenoperanden angibt, der Quelldatenelemente aufweist, und einen Zielspeicherort angibt. Jedes der Quelldatenelemente weist einen Quelldatenelementwert und eine Quelldatenelementposition auf. Eine Ausführungseinheit speichert in Reaktion auf den Befehl einen gepackten Ergebnisdatenoperanden, der Ergebnisdatenelemente aufweist, wovon jedes einen Ergebnisdatenelementwert und eine Ergebnisdatenelementposition aufweist. Jeder Ergebnisdatenelementwert ist eines der Folgenden: (1) gleich einer Quelldatenelementposition eines Quelldatenelements am nächsten an einem Ende des Quelloperanden, der einen Quelldatenelementwert aufweist, der gleich der Ergebnisdatenelementposition des Ergebnisdatenelements ist; und (2) ein Ersatzwert, wenn kein Quelldatenelement einen Quelldatenelementwert aufweist, der gleich der Ergebnisdatenelementposition des Ergebnisdatenelements ist.

9. 发明专利

GB2520853A Read and write masks update instruction for vectorization of recursive computations over independent data 未知
公开(公告)号：GB2520853A
公开(公告)日：2015-06-03
申请号：GB201500822
申请日：2013-06-12
申请人： INTEL CORP
发明人： PLOTNIKOV MIKHAIL , NARAIKIN ANDREY , HUGHES CHRISTOPHER J
IPC分类号： G06F9/30
摘要： A processor executes a mask update instruction to perform updates to a first mask register and a second mask register. A register file within the processor includes the first mask register and the second mask register. The processor includes execution circuitry to execute the mask update instruction. In response to the mask update instruction, the execution circuitry is to invert a given number of mask bits in the first mask register, and also to invert the given number of mask bits in the second mask register.

10. 发明公开

EP3238043A4 METHOD AND APPARATUS FOR PERFORMING CONFLICT DETECTION 审中-公开
公开(公告)号：EP3238043A4
公开(公告)日：2018-07-25
申请号：EP15873965
申请日：2015-11-23
申请人： INTEL CORP
发明人： HUGHES CHRISTOPHER J , OULD-AHMED-VALL ELMOUSTAPHA , VALENTINE ROBERT , GIRKAR MILIND B
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30047 , G06F9/30112 , G06F9/3834 , G06F9/3838
摘要： An apparatus and method are described for performing conflict detection operations. For example, one embodiment of a processor comprises: a first source vector register to store a first set of data elements; a second source vector register to store a second set of data elements; conflict detection logic to perform a specified comparison operation comparing each of the first set of data elements with specified data elements from the second set and generating a set of comparison results, the comparison operation to be selected from a group consisting of a greater than comparison, a less than comparison, a greater than or equal to comparison, a less than or equal to comparison, and a not equal to comparison.

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