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1. 发明申请

WO2007078538A3 COORDINATING ACCESS TO MEMORY LOCATIONS FOR HARDWARE TRANSACTIONAL MEMORY TRANSACTIONS AND SOFTWARE TRANSACTIONAL MEMORY TRANSACTIONS 审中-公开
标题翻译：协调对硬件交易记录交易和软件交易记录交易的存储位置访问
公开(公告)号：WO2007078538A3
公开(公告)日：2007-08-30
申请号：PCT/US2006046499
申请日：2006-12-05
申请人： INTEL CORP , ADL-TABATABAI ALI-REZA , SAHA BRATIN , HUDSON RICHARD L , AKKARY HAITHAM , RAJWAR RAVI
发明人： ADL-TABATABAI ALI-REZA , SAHA BRATIN , HUDSON RICHARD L , AKKARY HAITHAM , RAJWAR RAVI
IPC分类号： G06F9/52
CPC分类号： G06F9/467 , G06F12/0815 , G06F2212/507
摘要： Provided is a method, system, and program for coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions. A hardware transaction executing in hardware transactional memory initiates a request to access a memory location. A fault is returned to the hardware transaction request in response to an operation by one software transaction executing in a software transactional memory.
摘要翻译：提供了用于协调对硬件事务存储器事务和软件事务存储器事务的存储器位置的访问的方法，系统和程序。在硬件事务存储器中执行的硬件事务启动访问存储器位置的请求。响应于在软件事务存储器中执行的一个软件事务的操作，错误返回到硬件事务请求。

2. 发明申请

WO2006039201A3 CONTINUEL FLOW PROCESSOR PIPELINE 审中-公开
标题翻译：连续流动处理器管道
公开(公告)号：WO2006039201A3
公开(公告)日：2006-11-16
申请号：PCT/US2005034145
申请日：2005-09-21
申请人： INTEL CORP , AKKARY HAITHAM , RAJWAR RAVI , SRINIVASAN SRIKANTH
发明人： AKKARY HAITHAM , RAJWAR RAVI , SRINIVASAN SRIKANTH
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3863
摘要： Embodiments of the present invention relate to a system and method for comparatively increasing processor throughput and relieving pressure on the processor's scheduler and register file by diverting instructions dependent on long-latency operations from a flow of the processor pipeline and re-introducing them into the flow when the long-latency operations are completed. In this way, the instructions do not tie up resources and overall instruction throughput in the pipeline is comparatively increased.
摘要翻译：本发明的实施例涉及用于通过从处理器流水线的流转移取决于长等待时间操作的指令并将其重新引入流中来相对增加处理器吞吐量并减轻处理器的调度器和寄存器文件上的压力的系统和方法当长时间延迟操作完成时。这样，指令不会占用资源，并且管道中的整体指令吞吐量相对增加。

3. 发明申请

WO2012047600A3 THROTTLING INTEGRATED LINK 审中-公开
标题翻译： THROTTLING集成链接
公开(公告)号：WO2012047600A3
公开(公告)日：2012-08-16
申请号：PCT/US2011053335
申请日：2011-09-26
申请人： INTEL CORP , RAJWAR RAVI , MAYER ROBERT A , JOURDAN STEPHAN J , LOOI LILY PAO
发明人： RAJWAR RAVI , MAYER ROBERT A , JOURDAN STEPHAN J , LOOI LILY PAO
IPC分类号： G06F13/14 , G06F13/38
CPC分类号： G06F13/4059 , G06F1/3206 , G06F1/3253 , G06F13/4027 , G06F13/4286 , G06F13/4295 , Y02B60/1228 , Y02B60/1235 , Y02D10/151
摘要： Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.
摘要翻译：描述了用于节制与处理器集成在同一管芯上的接口的方法和设备。在一个实施例中，来自集成输入/输出集线器（例如，集成在与处理器相同的芯片上）的信号引起对耦合在IIO和输入/输出（IO）设备之间的链路的节制。其他实施例也被公开。

4. 发明申请

WO2008005687A3 GLOBAL OVERFLOW METHOD FOR VIRTUALIZED TRANSACTIONAL MEMORY 审中-公开
标题翻译：虚拟化事务存储器的全局溢出方法
公开(公告)号：WO2008005687A3
公开(公告)日：2008-02-21
申请号：PCT/US2007071711
申请日：2007-06-20
申请人： INTEL CORP , BARNES JESSE , RAJWAR RAVI
发明人： BARNES JESSE , RAJWAR RAVI
IPC分类号： G06F1/16
CPC分类号： G06F12/0815
摘要： A method and apparatus for virtualizing and/or extending transactional memory is described herein. Transactions are executed using local shared transactional memory, such as a cache memory. Upon overflowing the shared transactional memory, the transactional memory is virtualized and/or extended into a higher-level memory, such as a system memory. Upon an overflow event, such as an eviction of a cache line previously accessed during a currently pending transaction, an overflow flag is set to notify processors/cores that the transactional memory is to be virtualized in a global overflow table. A base address of the global overflow table is also potentially stored to reference the base of the global overflow table in the higher-level memory.
摘要翻译：这里描述了用于虚拟化和/或扩展交易存储器的方法和设备。事务使用本地共享事务内存（如高速缓存）执行。在共享事务存储器溢出时，事务存储器被虚拟化和/或扩展到诸如系统存储器的更高级存储器中。在发生溢出事件（例如在当前挂起的事务期间先前访问的高速缓存行的驱逐）时，设置溢出标志以通知处理器/核将事务存储器在全局溢出表中被虚拟化。全局溢出表的基地址也可能被存储来引用更高级别存储器中全局溢出表的基址。

5. 发明申请

WO2005041047A3 METHOD AND APPARATUS FOR EFFICIENT ORDERED STORES OVER AN INTERCONNECTION NETWORK 审中-公开
标题翻译：通过互连网络的高效有序存储的方法和设备
公开(公告)号：WO2005041047A3
公开(公告)日：2005-08-18
申请号：PCT/US2004034147
申请日：2004-10-15
申请人： INTEL CORP , CHARNEY MARK , RAJWAR RAVI , AHUJA PRITPAL , MATTINA MATT
发明人： CHARNEY MARK , RAJWAR RAVI , AHUJA PRITPAL , MATTINA MATT
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0811 , G06F12/0837 , G06F12/084
摘要： A physically distributed cache memory system includes an interconnection network, first level cache memory slices, and second level cache memory slices. The first level cache memory slices are coupled to the interconnection network to generate tagged ordered store requests. Each tagged ordered store requests has a tag including requestor identification and a store sequence token. The second level cache memory slices are coupled to the interconnection network to execute ordered store requests in-order across the physically distributed cache memory system in response to each tag of the tagged ordered store requests.
摘要翻译：物理分布式缓存存储器系统包括互连网络，第一级缓存存储器片和第二级缓存存储器片。第一级高速缓存存储器片被耦合到互连网络以生成带标签的有序存储请求。每个带标签的有序存储请求都有一个标签，包括请求者标识和存储顺序标记。第二级高速缓存存储器片被耦合到互连网络以响应于标记的有序存储请求的每个标签而在物理分布式高速缓存存储器系统上按顺序执行有序存储请求。

6. 发明申请

WO2011087590A2 SYNCHRONIZING SIMD VECTORS 审中-公开
标题翻译：同步SIMD矢量图
公开(公告)号：WO2011087590A2
公开(公告)日：2011-07-21
申请号：PCT/US2010058238
申请日：2010-11-29
申请人： INTEL CORP , RAJWAR RAVI , FORSYTH ANDREW T
发明人： RAJWAR RAVI , FORSYTH ANDREW T
CPC分类号： G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30087
摘要： A vector compare-and-exchange operation is performed by: decoding by a decoder in a processing device, a single instruction specifying a vector compare-and-exchange operation for a plurality of data elements between a first storage location, a second storage location, and a third storage location; issuing the single instruction for execution by an execution unit in the processing device; and responsive to the execution of the single instruction, comparing data elements from the first storage location to corresponding data elements in the second storage location; and responsive to determining a match exists, replacing the data elements from the first storage location with corresponding data elements from the third storage location.
摘要翻译：通过以下操作来执行向量比较和交换操作：通过处理设备中的解码器进行解码，指定在第一存储位置，第二存储位置和第二存储位置之间的多个数据元素的向量比较和交换操作的单个指令，和第三存储位置; 发出由处理装置中的执行单元执行的单个指令; 并且响应于所述单个指令的执行，将来自所述第一存储位置的数据元素与所述第二存储位置中的相应数据元素进行比较; 并且响应于确定匹配存在，用来自第三存储位置的相应数据元素从第一存储位置替换数据元素。

7. 发明申请

WO2012016085A3 LAST BRANCH RECORD INDICATORS FOR TRANSACTIONAL MEMORY 审中-公开
标题翻译：最后的分支记录指标用于事务记忆
公开(公告)号：WO2012016085A3
公开(公告)日：2012-05-31
申请号：PCT/US2011045797
申请日：2011-07-28
申请人： INTEL CORP , RAJWAR RAVI , KNAUTH LAURA A , LACHNER PETER , LAI KONRAD K
发明人： RAJWAR RAVI , KNAUTH LAURA A , LACHNER PETER , LAI KONRAD K
IPC分类号： G06F12/00
CPC分类号： G06F9/528 , G06F9/30101 , G06F9/38 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3857 , G06F9/3861 , G06F9/467 , G06F11/1407 , G06F11/3476 , G06F11/3636
摘要： In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括执行单元和至少一个最后分支记录（LBR）寄存器，以存储在程序执行期间采取的分支的地址信息。该寄存器可以进一步存储事务指示符以指示分支是否在事务存储器（TM）事务期间被采用。该寄存器可以进一步存储中止指示符以指示分支是否由事务中止引起。描述并要求保护其他实施例。

8. 发明申请

WO2007078647A3 PER-SET RELAXATION OF CACHE INCLUSION 审中-公开
标题翻译：缓存包含的集合放松
公开(公告)号：WO2007078647A3
公开(公告)日：2007-08-23
申请号：PCT/US2006047140
申请日：2006-12-06
申请人： INTEL CORP , RAJWAR RAVI , MATTINA MATTHEW
发明人： RAJWAR RAVI , MATTINA MATTHEW
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/084
摘要： A multi-core processor includes a plurality of processors and a shared cache. Cache control logic implements an inclusive cache scheme among the shared cache and the local caches for the processors. Counters are maintained to track instances, per set, when a processor chooses to delay eviction from the local cache. While the counter indicates that one or more delayed evictions are pending for a set, the cache control logic treats the set as non-inclusive, broadcasting foreign snoops to all of the local caches, regardless of whether the snoop hits in the shared cache. Other embodiments are also described and claimed.
摘要翻译：多核处理器包括多个处理器和共享高速缓存。高速缓存控制逻辑在共享高速缓存和处理器的本地高速缓存之间实现包容性高速缓存机制。当处理器选择延迟从本地缓存驱逐时，计数器被维护以追踪每个集合的实例。虽然计数器指示一个或多个延迟逐出正在等待一组，但是高速缓存控制逻辑将该组视为非包含，向所有本地高速缓存广播外部窥探，而不管窥探是否在共享高速缓存中命中。其他实施例也被描述和要求保护。

9. 发明专利

JP2009245452A Transactional memory execution utilizing virtual memory 有权
标题翻译：使用虚拟内存的交易记忆执行
公开(公告)号：JP2009245452A
公开(公告)日：2009-10-22
申请号：JP2009170142
申请日：2009-07-21
申请人： Intel Corp , インテルコーポレイション
发明人： RAJWAR RAVI , HERLIHY MAURICE
IPC分类号： G06F9/46 , G06F12/08 , G06F12/10
CPC分类号： G06F12/10 , G06F9/467 , G06F12/08
摘要： PROBLEM TO BE SOLVED: To enable transactional memory execution utilizing virtual memory without hardware support.
SOLUTION: An apparatus comprises: a processor including a local transactional cache; and a resource manager responsive to a transactional memory transaction request from a requesting thread to determine whether the local transactional cache is capable of accommodating the transactional memory transaction request. If the transactional memory transaction request can be accommodated, the local transactional cache performs the transactional memory transaction. However, if the transactional memory transaction request cannot be accommodated, the transactional memory transaction request is overflowed into an application virtual address space associated with the requesting thread.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：使用没有硬件支持的虚拟内存来实现事务性内存执行。解决方案：一种装置，包括：处理器，包括本地事务高速缓存; 以及响应于来自请求线程的事务存储器事务请求的资源管理器，以确定本地事务高速缓存是否能够容纳事务存储器事务请求。如果可以容纳事务内存事务请求，则本地事务高速缓存执行事务内存事务。然而，如果不能容纳事务性存储器事务请求，则事务存储器事务请求被溢出到与请求线程相关联的应用虚拟地址空间中。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2014059902A Synchronizing simd vectors 有权
标题翻译：同步SIMD矢量图
公开(公告)号：JP2014059902A
公开(公告)日：2014-04-03
申请号：JP2013240725
申请日：2013-11-21
申请人： Intel Corp , インテル・コーポレーション
发明人： RAJWAR RAVI , FORSYTH ANDREW T
IPC分类号： G06F9/52 , G06F17/16
CPC分类号： G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30087
摘要： PROBLEM TO BE SOLVED: To provide instructions that enable a read-modify-write operation to be executed as an indivisible operation for vector data.SOLUTION: A vector compare-and-exchange operation is performed by: decoding, by a decoder in a processing device, a single instruction specifying a vector compare-and-exchange operation for a plurality of data elements between a first storage location, a second storage location, and a third storage location; issuing the single instruction for execution by an execution unit in the processing device; in response to the execution of the single instruction, comparing data elements from the first storage location to corresponding data elements in the second storage location; and, in response to determining if a match exists, replacing the data elements from the first storage location with corresponding data elements from the third storage location.
摘要翻译：要解决的问题：提供使读取 - 修改 - 写入操作能够作为向量数据的不可分割的操作来执行的指令。解决方案：矢量比较和交换操作通过解码器在处理中进行解码指定在第一存储位置，第二存储位置和第三存储位置之间的多个数据元素的矢量比较和交换操作的单个指令; 发出由处理装置中的执行单元执行的单个指令; 响应于所述单个指令的执行，将来自所述第一存储位置的数据元素与所述第二存储位置中的相应数据元素进行比较; 并且响应于确定是否存在匹配，用来自第三存储位置的相应数据元素替换来自第一存储位置的数据元素。

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