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1. 发明申请

WO0125886A9 POWER MANAGEMENT METHOD FOR A COMPUTER SYSTEM HAVING A HUB INTERFACE ARCHITECTURE 审中-公开
标题翻译：具有集线器接口结构的计算机系统的电源管理方法
公开(公告)号：WO0125886A9
公开(公告)日：2002-08-01
申请号：PCT/US0040998
申请日：2000-09-26
申请人： INTEL CORP , HARRIMAN DAVID J , POISNER DAVID I , RABE JEFF
发明人： HARRIMAN DAVID J , POISNER DAVID I , RABE JEFF
IPC分类号： G06F1/32
CPC分类号： G06F1/3253 , G06F1/3203 , Y02D10/151
摘要： According to one embodiment, a computer system includes a Central Processing Unit (CPU), a hub agent and a hub interface coupled to the first hub agent. The computer system transitions from a first power state to a second power state upon the CPU determining that no requests are pending to access the first hub interface.
摘要翻译：根据一个实施例，一种计算机系统包括中央处理单元（CPU），耦合到第一集线器代理的集线器代理和集线器接口。当CPU确定没有请求等待接入第一集线器接口时，计算机系统从第一功率状态转换到第二功率状态。

2. 发明授权

US6374321B2 Mechanisms for converting address and data signals to interrupt message signals 有权
标题翻译：将地址和数据信号转换为中断消息信号的机制
公开(公告)号：US6374321B2
公开(公告)日：2002-04-16
申请号：US42868299
申请日：1999-10-27
申请人： INTEL CORP
发明人： PAWLOWSKI STEPHEN S , ABRAMSON DARREN L , POISNER DAVID I , MISHRA KISHORE K
IPC分类号： G06F13/24 , G06F9/46
CPC分类号： G06F13/24
摘要： In some embodiments, the invention includes an apparatus including a host bridge coupled to a processor bus. The apparatus also includes an I/O bridge coupled to the host bridge, the I/O bridge including ports to receive an interrupt request signal in the form of address signals and data signals. Decode logic receives at least some of the address signals and data signals and to provide a decoded signal responsive thereto. A redirection table includes a send pending bit that is set responsive to the decoded signal.
摘要翻译：在一些实施例中，本发明包括一种包括耦合到处理器总线的主桥的装置。该装置还包括耦合到主桥的I / O桥，I / O桥包括用于接收地址信号和数据信号形式的中断请求信号的端口。解码逻辑接收至少一些地址信号和数据信号，并且响应于此提供解码信号。重定向表包括响应于解码信号设置的发送挂起位。

3. 发明专利

AU3369497A System for controlling access to a register mapped to an i/o address space of a computer system 未知
公开(公告)号：AU3369497A
公开(公告)日：1998-01-07
申请号：AU3369497
申请日：1997-05-22
申请人： INTEL CORP
发明人： POISNER DAVID I
IPC分类号： G06F13/10 , G06F9/38 , G06F15/00
摘要： A method of providing access to an input/output (I/O)-mapped register of a computer system is described. The computer system includes a processor operable in a system management mode (SMM), in which the processor accesses a dedicated system management memory space, a real mode, a protected mode and a virtual 8086 mode. The method includes the steps of firstly receiving an access request at the I/O-mapped register. Logic circuitry associated with the I/O-mapped register then determines whether the processor is operating in SMM by examining the status of a system management interrupt acknowledge (SMIACT#) output of the processor. If the logic circuitry determines that the processor is operating in SMM, a first, unrestricted type of access by the processor to the I/O-mapped register is provided. Alternatively, if the logic circuitry determines that the processor is not operating in SMM, a second, restricted type of access by the processor to the I/O-mapped register is provided. If the first, unrestricted type of access is provided to the processor, it performs an operation, under the direction of code stored in the dedicated system management memory address space, on the contents of the I/O-mapped register.

4. 发明申请

WO2015088626A3 BIOMETRIC SENSORS FOR PERSONAL DEVICES 审中-公开
标题翻译：用于个人设备的生物量传感器
公开(公告)号：WO2015088626A3
公开(公告)日：2015-08-13
申请号：PCT/US2014057581
申请日：2014-09-26
申请人： INTEL CORP , PANT MONDIRA D , ABDELMONEUM MOHAMED A , KARNIK TANAY , PISENTI STEPHEN , POISNER DAVID I , MAHAMEED RASHED
发明人： PANT MONDIRA D , ABDELMONEUM MOHAMED A , KARNIK TANAY , PISENTI STEPHEN , POISNER DAVID I , MAHAMEED RASHED
IPC分类号： G06K9/00 , G06F21/32
CPC分类号： G01N29/265 , G01N2291/106 , G06F21/32 , G06F2221/2111 , G06K9/0002 , Y10T29/49005
摘要： Methods and systems may provide for a system having a flexible substrate, an ultrasonic transducer array coupled to the flexible substrate and a processor coupled to the ultrasonic transducer array. The processor may identify a fingerprint based on a signal from the ultrasonic transducer array. The system may also include an external component having a curved profile, wherein the ultrasonic transducer array is embedded in the external component and includes a read surface that conforms to the curved profile. In one example, the external component includes a button having a function that is separate from identification of the fingerprint.
摘要翻译：方法和系统可以提供具有柔性衬底，耦合到柔性衬底的超声换能器阵列和耦合到超声换能器阵列的处理器的系统。处理器可以基于来自超声换能器阵列的信号识别指纹。该系统还可以包括具有弯曲轮廓的外部部件，其中超声换能器阵列嵌入在外部部件中并且包括符合弯曲轮廓的读取表面。在一个示例中，外部组件包括具有与指纹的识别分离的功能的按钮。

5. 发明申请

WO0125886A2 POWER MANAGEMENT METHOD FOR A COMPUTER SYSTEM HAVING A HUB INTERFACE ARCHITECTURE 审中-公开
标题翻译：具有集线器接口架构的计算机系统的电源管理方法
公开(公告)号：WO0125886A2
公开(公告)日：2001-04-12
申请号：PCT/US0040998
申请日：2000-09-26
申请人： INTEL CORP , HARRIMAN DAVID J , POISNER DAVID I , RABE JEFF
发明人： HARRIMAN DAVID J , POISNER DAVID I , RABE JEFF
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3253 , G06F1/3203 , Y02D10/151
摘要： According to one embodiment, a computer system includes a Central Processing Unit (CPU), a hub agent and a hub interface coupled to the first hub agent. The computer system transitions from a first power state to a second power state upon the CPU determining that no requests are pending to access the first hub interface.
摘要翻译：根据一个实施例，计算机系统包括中央处理单元（CPU），集线器代理和耦合到第一集线器代理的集线器接口。当CPU确定没有请求正在等待访问第一集线器接口时，计算机系统从第一电力状态转换到第二电力状态。

6. 发明专利

DE19882696B4 未知
公开(公告)号：DE19882696B4
公开(公告)日：2007-05-24
申请号：DE19882696
申请日：1998-07-07
申请人： INTEL CORP
发明人： GAFKEN ANDREW H , BENNETT JOSEPH A , POISNER DAVID I
IPC分类号： G06F13/10 , G06F12/00 , G06F13/38 , G06F13/16 , G06F13/42
摘要： A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.

7. 发明专利

AT331245T 未知
公开(公告)号：AT331245T
公开(公告)日：2006-07-15
申请号：AT00982616
申请日：2000-09-26
申请人： INTEL CORP
发明人： HARRIMAN DAVID J , POISNER DAVID I , RABE JEFF
IPC分类号： G06F1/32 , G06F1/26
摘要： According to one embodiment, a computer system includes a Central Processing Unit (CPU), a hub agent and a hub interface coupled to the first hub agent. The computer system transitions from a first power state to a second power state upon the CPU determining that no requests are pending to access the first hub interface.

8. 发明专利

AU1962401A Power management method for a computer system having a hub interface architecture 未知
公开(公告)号：AU1962401A
公开(公告)日：2001-05-10
申请号：AU1962401
申请日：2000-09-26
申请人： INTEL CORP
发明人： HARRIMAN DAVID J , POISNER DAVID I , RABE JEFF
IPC分类号： G06F1/32 , G06F1/26
摘要： According to one embodiment, a computer system includes a Central Processing Unit (CPU), a hub agent and a hub interface coupled to the first hub agent. The computer system transitions from a first power state to a second power state upon the CPU determining that no requests are pending to access the first hub interface.

9. 发明专利

HK1045201B 用於備有一轂盤介面架構電腦系統的電力管理方法未知
公开(公告)号：HK1045201B
公开(公告)日：2006-11-10
申请号：HK02106552
申请日：2002-09-05
申请人： INTEL CORP
发明人： HARRIMAN DAVID J , POISNER DAVID I , RABE JEFF
IPC分类号： G06F20060101 , G06F1/32

10. 发明专利

HK1045201A1 Power management method for a computer system having a hub interface architecture 未知
公开(公告)号：HK1045201A1
公开(公告)日：2002-11-15
申请号：HK02106552
申请日：2002-09-05
申请人： INTEL CORP
发明人： HARRIMAN DAVID J , POISNER DAVID I , RABE JEFF
IPC分类号： G06F20060101 , G06F1/32
摘要： According to one embodiment, a computer system includes a Central Processing Unit (CPU), a hub agent and a hub interface coupled to the first hub agent. The computer system transitions from a first power state to a second power state upon the CPU determining that no requests are pending to access the first hub interface.

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