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1. 发明申请

WO2009031052A3 ZERO-CAPACITOR (FLOATING BODY) RANDOM ACCESS MEMORY CIRCUITS WITH POLYCIDE WORD LINES AND MANUFACTURING METHODS THEREFOR 审中-公开
标题翻译：零电容（浮动体）带多边形字线的随机存取电路及其制造方法
公开(公告)号：WO2009031052A3
公开(公告)日：2009-08-06
申请号：PCT/IB2008003284
申请日：2008-03-21
申请人： INNOVATIVE SILICON SA , FAZAN PIERRE
发明人： FAZAN PIERRE
IPC分类号： H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/12 , H01L29/78
CPC分类号： H01L27/10805 , H01L21/84 , H01L27/108 , H01L27/10844 , H01L27/10847 , H01L27/1203 , H01L29/7841
摘要： Embodiments of a manufacturing process flow for producing memory devices that can achieve bit cell sizes on the order of 4F2 or 5F2, and that can be applied to common source/drain, separate source/drain, or common source only or common drain only transistor arrays. Active area and word line patterns are formed as perpendicularly-arranged straight lines on a Silicon-on-Insulator substrate. The intersections of the active area and spaces between word lines define contact areas for the connection of vias and metal line layers. Insulative spacers are used to provide an etch mask pattern that allows the selective etching of contact areas as a series of linear trenches, thus facilitating straight line lithography techniques. Embodiments of the manufacturing process remove first layer metal (metal-1) islands and form elongated vias, in a succession of processing steps to build dense memory arrays.
摘要翻译：用于生产可以实现4F2或5F2的数量级的位单元大小的存储器件的制造工艺流程的实施例，并且可以应用于公共源极/漏极，单独的源极/漏极或仅公共源极或仅公共的仅漏极晶体管阵列。有源区域和字线图案在绝缘体上硅衬底上形成为垂直布置的直线。活动区域和字线间的交点定义用于连接通孔和金属线层的接触区域。使用绝缘间隔物来提供蚀刻掩模图案，其允许将接触区域选择性地蚀刻为一系列线性沟槽，从而便于直线光刻技术。制造过程的实施例在连续的处理步骤中去除第一层金属（金属-1）岛并形成细长的通孔以构建密集的存储器阵列。

2. 发明申请

WO2005029499A2 LOW POWER PROGRAMMING TECHNIQUE FOR A FLOATING BODY MEMORY TRANSISTOR, MEMORY CELL, AND MEMORY ARRAY 审中-公开
标题翻译：浮动体内存晶体管，存储单元和存储阵列的低功耗编程技术
公开(公告)号：WO2005029499A2
公开(公告)日：2005-03-31
申请号：PCT/IB2004003721
申请日：2004-09-23
申请人： INNOVATIVE SILICON SA , FAZAN PIERRE , OKHONIN SERGUEI
发明人： FAZAN PIERRE , OKHONIN SERGUEI
IPC分类号： G11C11/404 , H01L27/108 , G11C16/02
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State "0" in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State "0" in the memory cell while the electrically floating body transistor is in the "OFF" state or substantially "OFF" state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.
摘要翻译：这里描述和说明了许多发明。一方面，本发明涉及将数据写入或编程到存储器单元中的存储器单元，架构和/或阵列和/或技术（例如，写入或编程逻辑低或状态“0”的技术在这方面，本发明在电浮动体晶体管处于“关”状态或基本上“关”的情况下，在存储单元中编程逻辑低或状态“0” 状态（例如，当器件在源极和漏极之间没有（或几乎不存在）通道和/或沟道电流）时，可以对存储单元进行编程，从而使存储单元几乎没有电流/功耗电浮体晶体管和/或具有多个电浮体晶体管的存储器阵列。

3. 发明专利

AT366983T 未知
公开(公告)号：AT366983T
公开(公告)日：2007-08-15
申请号：AT04787565
申请日：2004-09-23
申请人： INNOVATIVE SILICON SA
发明人： FAZAN PIERRE , OKHONIN SERGUEI
IPC分类号： G11C11/404 , H01L27/108
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State "0" in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State "0" in the memory cell while the electrically floating body transistor is in the "OFF" state or substantially "OFF" state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.

4. 发明专利

DE602004007536D1 未知
公开(公告)号：DE602004007536D1
公开(公告)日：2007-08-23
申请号：DE602004007536
申请日：2004-09-23
申请人： INNOVATIVE SILICON SA
发明人： FAZAN PIERRE , OKHONIN SERGUEI
IPC分类号： G11C11/404 , H01L27/108
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State "0" in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State "0" in the memory cell while the electrically floating body transistor is in the "OFF" state or substantially "OFF" state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.

5. 发明专利

DE602004007536T2 未知
公开(公告)号：DE602004007536T2
公开(公告)日：2008-03-20
申请号：DE602004007536
申请日：2004-09-23
申请人： INNOVATIVE SILICON SA
发明人： FAZAN PIERRE , OKHONIN SERGUEI
IPC分类号： G11C11/404 , H01L27/108
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State "0" in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State "0" in the memory cell while the electrically floating body transistor is in the "OFF" state or substantially "OFF" state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.

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