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1. 发明申请

WO03088322A2 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO03088322A2
公开(公告)日：2003-10-23
申请号：PCT/EP0302748
申请日：2003-03-17
申请人： INNOVATIVE SILICON SA , FAZAN PIERRE CHRISTOPHE , OKHONIN SERGUEI
发明人： FAZAN PIERRE CHRISTOPHE , OKHONIN SERGUEI
IPC分类号： H01L21/8242 , H01L27/108 , H01L27/12 , H01L29/739 , H01L29/786 , H01L29/788 , H01L21/00
CPC分类号： H01L29/78696 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/10873 , H01L27/1203 , H01L29/7391 , H01L29/7841 , H01L29/78648 , H01L29/7881
摘要： A semiconductor device such as a DPAM memory device is disclosed. A, Substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semiconductor layer (16) has source (18) and drain (20) regions formed therein to define bodies (22) of respective field effect transistors. The box region (38) is more heavily doped than the adjacent body (22), but less highly doped than the corresponding source (18) and drain (20), and modifies the valence and/or conduction band of the body (22) to increase the amount of electrical charge which can be stored in the body (22).
摘要翻译：公开了诸如DPAM存储器件的半导体器件。 A，半导体材料的基板（12）设置有箱形区域（38）形式的能带修改装置，并被绝缘层（14）覆盖。半导体层（16）具有形成在其中的源极（18）和漏极（20）区域，以限定各个场效应晶体管的主体（22）。盒区域（38）比相邻体（22）更重掺杂，但是比相应的源极（18）和漏极（20）掺杂得较少，并且改变了本体（22）的价态和/或导带，以增加可以存储在身体（22）中的电荷量。

2. 发明申请

WO2007098044A3 MULTI-BIT MEMORY CELL HAVING ELECTRICALLY FLOATING BODY TRANSISTOR, AND METHOD OF PROGRAMMING AND READING SAME 审中-公开
标题翻译：具有电浮标体晶体管的多位存储单元及其编程和读取方法
公开(公告)号：WO2007098044A3
公开(公告)日：2008-10-16
申请号：PCT/US2007004163
申请日：2007-02-15
申请人： INNOVATIVE SILICON SA , CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
发明人： CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
IPC分类号： G11C11/34
CPC分类号： H01L29/7841 , G11C7/1006 , G11C7/16 , G11C11/404 , G11C11/565 , G11C2211/4016
摘要： Multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc ) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory)
摘要翻译：用于读取，写入和/或操作具有一个或多个电浮动体晶体管的多位存储单元（以及具有多个这样的存储单元的存储单元阵列）的多位存储单元和电路和技术，其中电荷是存储在电浮体晶体管的体区中。多位存储器单元存储多于一个的数据位（例如，二，三，四，五，六等）和/或两个以上的数据状态（例如，三，四，五，六等等）值得注意的是，存储单元阵列可以包括集成电路器件的一部分，例如逻辑器件（例如，微处理器）或存储器件的一部分（例如，分立存储器）

3. 发明专利

AT354852T 未知
公开(公告)号：AT354852T
公开(公告)日：2007-03-15
申请号：AT02077116
申请日：2002-05-29
申请人： INNOVATIVE SILICON SA , ECOLE POLYTECH
发明人： FAZAN PIERRE CHRISTOPHE , OKHONIN SERGUEI
IPC分类号： G11C11/404 , G11C11/406

4. 发明申请

WO2008090475A3 FLOATING-BODY DRAM TRANSISTOR COMPRISING SOURCE/DRAIN REGIONS SEPARATED FROM THE GATED BODY REGION 审中-公开
标题翻译：包含源自区域的源/排放区域的浮动体DRAM晶体管
公开(公告)号：WO2008090475A3
公开(公告)日：2009-04-30
申请号：PCT/IB2008000980
申请日：2008-01-24
申请人： INNOVATIVE SILICON SA , OKHONIN SERGUEI
发明人： OKHONIN SERGUEI
IPC分类号： H01L27/108 , G11C11/404 , H01L29/78
CPC分类号： H01L27/1203 , G11C7/00 , G11C11/40 , G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/1207 , H01L29/7841
摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region (18) and a gate (16) is disposed over a first portion (18-1) of the body region. The device includes a source region (20) adjoining a second portion (18-2) of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region (22) adjoining a third portion (18-3) of the body region, the third portion adjacent the first portion and separating the drain region from the first portion.
摘要翻译：描述了包括其的电路的半导体器件及其操作方法。该装置包括电浮动体区域（18），并且在身体区域的第一部分（18-1）之上设置有栅极（16）。该装置包括与本体区域的第二部分（18-2）邻接的源极区域（20），邻近第一部分的第二部分并且将源区域与第一部分分离。所述装置包括邻接所述主体区域的第三部分（18-3）的漏极区域（22），所述第三部分与所述第一部分相邻并且将所述漏极区域与所述第一部分分开。

5. 发明申请

WO2007098044A8 MULTI-BIT MEMORY CELL HAVING ELECTRICALLY FLOATING BODY TRANSISTOR, AND METHOD OF PROGRAMMING AND READING SAME 审中-公开
标题翻译：具有电浮标体晶体管的多位存储单元及其编程和读取方法
公开(公告)号：WO2007098044A8
公开(公告)日：2007-11-29
申请号：PCT/US2007004163
申请日：2007-02-15
申请人： INNOVATIVE SILICON SA , CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
发明人： CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
IPC分类号： G11C11/34
CPC分类号： H01L29/7841 , G11C7/1006 , G11C7/16 , G11C11/404 , G11C11/565 , G11C2211/4016
摘要： There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc.) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory).
摘要翻译：这里描述的许多发明以及这些发明的许多方面和实施例，例如多位存储器单元以及用于读取，写入和/或操作多位存储器单元（以及具有多个这样的存储单元）具有一个或多个电浮动体晶体管，其中电荷存储在电浮体晶体管的体区中。多比特存储单元存储多于一个的数据位（例如，两个，三个，四个，五个，六个等等）和/或两个以上的数据状态（例如，三个，四个，五个，六个等等）值得注意的是，存储单元阵列可以包括集成电路器件的一部分，例如逻辑器件（例如，微处理器）或存储器件（例如，分立存储器）的一部分。

6. 发明申请

WO2005029499A2 LOW POWER PROGRAMMING TECHNIQUE FOR A FLOATING BODY MEMORY TRANSISTOR, MEMORY CELL, AND MEMORY ARRAY 审中-公开
标题翻译：浮动体内存晶体管，存储单元和存储阵列的低功耗编程技术
公开(公告)号：WO2005029499A2
公开(公告)日：2005-03-31
申请号：PCT/IB2004003721
申请日：2004-09-23
申请人： INNOVATIVE SILICON SA , FAZAN PIERRE , OKHONIN SERGUEI
发明人： FAZAN PIERRE , OKHONIN SERGUEI
IPC分类号： G11C11/404 , H01L27/108 , G11C16/02
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State "0" in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State "0" in the memory cell while the electrically floating body transistor is in the "OFF" state or substantially "OFF" state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.
摘要翻译：这里描述和说明了许多发明。一方面，本发明涉及将数据写入或编程到存储器单元中的存储器单元，架构和/或阵列和/或技术（例如，写入或编程逻辑低或状态“0”的技术在这方面，本发明在电浮动体晶体管处于“关”状态或基本上“关”的情况下，在存储单元中编程逻辑低或状态“0” 状态（例如，当器件在源极和漏极之间没有（或几乎不存在）通道和/或沟道电流）时，可以对存储单元进行编程，从而使存储单元几乎没有电流/功耗电浮体晶体管和/或具有多个电浮体晶体管的存储器阵列。

7. 发明专利

DE60218283T2 未知
公开(公告)号：DE60218283T2
公开(公告)日：2007-11-15
申请号：DE60218283
申请日：2002-05-29
申请人： INNOVATIVE SILICON SA , ECOLE POLYTECH
发明人： FAZAN PIERRE CHRISTOPHE , OKHONIN SERGUEI
IPC分类号： G11C11/404 , G11C11/406

8. 发明专利

AU2003226646A1 SEMICONDUCTOR DEVICE 未知
公开(公告)号：AU2003226646A1
公开(公告)日：2003-10-27
申请号：AU2003226646
申请日：2003-03-17
申请人： INNOVATIVE SILICON SA
发明人： FAZAN PIERRE CHRISTOPHE , OKHONIN SERGUEI
IPC分类号： H01L21/8242 , H01L27/108 , H01L27/12 , H01L29/739 , H01L29/786 , H01L29/788 , H01L21/00

9. 发明专利

DE602004007536T2 未知
公开(公告)号：DE602004007536T2
公开(公告)日：2008-03-20
申请号：DE602004007536
申请日：2004-09-23
申请人： INNOVATIVE SILICON SA
发明人： FAZAN PIERRE , OKHONIN SERGUEI
IPC分类号： G11C11/404 , H01L27/108
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State "0" in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State "0" in the memory cell while the electrically floating body transistor is in the "OFF" state or substantially "OFF" state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.

10. 发明专利

AU2003226646A8 Semiconductor device 未知
公开(公告)号：AU2003226646A8
公开(公告)日：2003-10-27
申请号：AU2003226646
申请日：2003-03-17
申请人： INNOVATIVE SILICON SA
发明人： FAZAN PIERRE CHRISTOPHE , OKHONIN SERGUEI
IPC分类号： H01L21/8242 , H01L27/108 , H01L27/12 , H01L29/739 , H01L29/786 , H01L29/788

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