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1. 发明申请

WO2007098044A8 MULTI-BIT MEMORY CELL HAVING ELECTRICALLY FLOATING BODY TRANSISTOR, AND METHOD OF PROGRAMMING AND READING SAME 审中-公开
标题翻译：具有电浮标体晶体管的多位存储单元及其编程和读取方法
公开(公告)号：WO2007098044A8
公开(公告)日：2007-11-29
申请号：PCT/US2007004163
申请日：2007-02-15
申请人： INNOVATIVE SILICON SA , CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
发明人： CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
IPC分类号： G11C11/34
CPC分类号： H01L29/7841 , G11C7/1006 , G11C7/16 , G11C11/404 , G11C11/565 , G11C2211/4016
摘要： There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc.) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory).
摘要翻译：这里描述的许多发明以及这些发明的许多方面和实施例，例如多位存储器单元以及用于读取，写入和/或操作多位存储器单元（以及具有多个这样的存储单元）具有一个或多个电浮动体晶体管，其中电荷存储在电浮体晶体管的体区中。多比特存储单元存储多于一个的数据位（例如，两个，三个，四个，五个，六个等等）和/或两个以上的数据状态（例如，三个，四个，五个，六个等等）值得注意的是，存储单元阵列可以包括集成电路器件的一部分，例如逻辑器件（例如，微处理器）或存储器件（例如，分立存储器）的一部分。

2. 发明申请

WO2004102576A3 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING SAME 审中-公开
公开(公告)号：WO2004102576A3
公开(公告)日：2004-11-25
申请号：PCT/US2004/014691
申请日：2004-05-11
申请人： INNOVATIVE SILICON, INC. , ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL) , FERRANT, Richard , OKHONIN, Serguei , CARMAN, Eric , BRON, Michel
发明人： FERRANT, Richard , OKHONIN, Serguei , CARMAN, Eric , BRON, Michel
IPC分类号： G11C11/00
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

3. 发明申请

WO2007098044A3 MULTI-BIT MEMORY CELL HAVING ELECTRICALLY FLOATING BODY TRANSISTOR, AND METHOD OF PROGRAMMING AND READING SAME 审中-公开
标题翻译：具有电浮标体晶体管的多位存储单元及其编程和读取方法
公开(公告)号：WO2007098044A3
公开(公告)日：2008-10-16
申请号：PCT/US2007004163
申请日：2007-02-15
申请人： INNOVATIVE SILICON SA , CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
发明人： CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
IPC分类号： G11C11/34
CPC分类号： H01L29/7841 , G11C7/1006 , G11C7/16 , G11C11/404 , G11C11/565 , G11C2211/4016
摘要： Multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc ) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory)
摘要翻译：用于读取，写入和/或操作具有一个或多个电浮动体晶体管的多位存储单元（以及具有多个这样的存储单元的存储单元阵列）的多位存储单元和电路和技术，其中电荷是存储在电浮体晶体管的体区中。多位存储器单元存储多于一个的数据位（例如，二，三，四，五，六等）和/或两个以上的数据状态（例如，三，四，五，六等等）值得注意的是，存储单元阵列可以包括集成电路器件的一部分，例如逻辑器件（例如，微处理器）或存储器件的一部分（例如，分立存储器）

4. 发明申请

WO2008085701A2 METHOD AND APPARATUS FOR VARIABLE MEMORY CELL REFRESH 审中-公开
标题翻译：用于可变存储器单元刷新的方法和装置
公开(公告)号：WO2008085701A2
公开(公告)日：2008-07-17
申请号：PCT/US2007/088529
申请日：2007-12-21
申请人： INNOVATIVE SILICON S.A. , FISCH, David , CARMAN, Eric
发明人： FISCH, David , CARMAN, Eric
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C2207/104 , G11C2211/4016 , G11C2211/4067
摘要： The embodiments described herein allow a system using a memory array, or the memory itself, to more efficiently control refresh intervals. This reduces standby current and the overhead associated with refresh operations. One embodiment includes a variable analog refresh signal generation circuit that initiates a refresh operation on one or more memory cells of a memory array. The circuit integrates a refresh timer element with an event signal generator such that a refresh interval as defined by the refresh timer element is changed when events are detected that may change the data retention time of one or more memory cells. In various embodiments, one or more of the circuits is placed to monitor an entire memory array, different sub-arrays, or different portions of different sub-arrays. This allows additional refresh operations to be closely tied to actual events, thus increasing overall efficiency.
摘要翻译：这里描述的实施例允许使用存储器阵列或存储器本身的系统更有效地控制刷新间隔。这减少了备用电流和与刷新操作相关的开销。一个实施例包括可变模拟刷新信号产生电路，其启动对存储器阵列的一个或多个存储器单元的刷新操作。电路将刷新定时器元件与事件信号发生器集成，使得当检测到可能改变一个或多个存储器单元的数据保持时间的事件时，刷新定时器元件定义的刷新间隔被改变。在各种实施例中，放置一个或多个电路以监视整个存储器阵列，不同子阵列或不同子阵列的不同部分。这允许额外的刷新操作与实际事件紧密相关，从而提高整体效率。

5. 发明申请

WO2007126830A3 MEMORY ARRAY HAVING A PROGRAMMABLE WORD LENGTH, AND METHOD OF OPERATING SAME 审中-公开
公开(公告)号：WO2007126830A3
公开(公告)日：2007-11-08
申请号：PCT/US2007/007591
申请日：2007-03-29
申请人： INNOVATIVE SILICON S.A. , CARMAN, Eric
发明人： CARMAN, Eric
IPC分类号： G05B99/00 , G06N7/00
摘要： A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array. In one aspect, write and/or read operations may be performed with respect to selected memory cells of a selected row of the memory array, while unselected memory cells of the selected row are undisturbed.

6. 发明申请

WO2006065698A8 SENSE AMPLIFIER CIRCUITRY AND ARCHITECTURE TO WRITE DATA INTO AND/OR READ DATA FROM MEMORY CELLS 审中-公开
标题翻译： SENSE放大器电路和架构将数据写入和/或从存储器单元读取数据
公开(公告)号：WO2006065698A8
公开(公告)日：2006-08-17
申请号：PCT/US2005044791
申请日：2005-12-12
申请人： WALLER WILLIAM KENNETH , CARMAN ERIC
发明人： WALLER WILLIAM KENNETH , CARMAN ERIC
IPC分类号： G11C11/24
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/14 , G11C11/4099 , G11C2211/4013 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A technique of, and circuitry for sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, sense amplifier circuitry is relatively compact and pitched to the array of memory cells such that a row of data may be read, sampled and/or sensed during a read operation. In this regard, an entire row of memory cells may be accessed and read during one operation which, relative to at least architecture employing multiplexer circuitry, may minimize, enhance and/or improve read latency and read access time, memory cell disturbance and/or simplify the control of the sense amplifier circuitry and access thereof. The sense amplifier circuitry may include write back circuitry to modify or "re-store" the data read, sampled and/or sensed during a read operation and/or a refresh operation in the context of a DRAM array. The sense amplifier circuitry of this embodiment restores and/or refreshes data in an entire row of volatile and/or destructive read type memory cells in parallel. This architecture may minimize, enhance and/or improve write back and read latency parameters, relative to at least architecture employing multiplexer circuitry. Also, data that has been read, sampled and/or sensed by the sense amplifier circuitry during a read operation may be modified before being written back to one or more of the memory cells of the selected row of the array of memory cells.
摘要翻译：用于采样，感测，读取和/或确定存储器单元阵列的存储器单元的数据状态的技术和电路（例如，具有由电浮体晶体管组成的多个存储单元的存储单元阵列）。在一个实施例中，感测放大器电路相对紧凑并且倾斜到存储器单元阵列，使得在读取操作期间可以读取，采样和/或感测数据行。在这方面，可以在一个操作期间访问和读取整行存储器单元，其相对于至少采用多路复用器电路的架构可以最小化，增强和/或改善读延迟和读访问时间，存储器单元的干扰和/或简化了读出放大器电路的控制及其访问。读出放大器电路可以包括写回电路，以在DRAM阵列的上下文中修改或“重新存储”在读取操作期间和/或刷新操作期间读取，采样和/或感测的数据。该实施例的读出放大器电路并行地在整行的易失性和/或破坏性读取型存储器单元中恢复和/或刷新数据。相对于至少采用多路复用器电路的架构，该架构可以最小化，增强和/或改进回写和读取延迟参数。此外，读取操作期间由读出放大器电路读取，采样和/或感测的数据可以在被写回存储器单元阵列的选定行的一个或多个存储器单元之前被修改。

7. 发明申请

WO2008085701A3 METHOD AND APPARATUS FOR VARIABLE MEMORY CELL REFRESH 审中-公开
标题翻译：用于可变存储器单元刷新的方法和装置
公开(公告)号：WO2008085701A3
公开(公告)日：2009-02-12
申请号：PCT/US2007088529
申请日：2007-12-21
申请人： INNOVATIVE SILICON SA , FISCH DAVID , CARMAN ERIC
发明人： FISCH DAVID , CARMAN ERIC
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C2207/104 , G11C2211/4016 , G11C2211/4067
摘要： The embodiments described herein allow a system using a memory array, or the memory itself, to more efficiently control refresh intervals. This reduces standby current and the overhead associated with refresh operations. One embodiment includes a variable analog refresh signal generation circuit that initiates a refresh operation on one or more memory cells of a memory array. The circuit integrates a refresh timer element with an event signal generator such that a refresh interval as defined by the refresh timer element is changed when events are detected that may change the data retention time of one or more memory cells. In various embodiments, one or more of the circuits is placed to monitor an entire memory array, different sub-arrays, or different portions of different sub-arrays. This allows additional refresh operations to be closely tied to actual events, thus increasing overall efficiency.
摘要翻译：这里描述的实施例允许使用存储器阵列或存储器本身的系统更有效地控制刷新间隔。这减少了备用电流和与刷新操作相关的开销。一个实施例包括可变模拟刷新信号产生电路，其启动对存储器阵列的一个或多个存储器单元的刷新操作。电路将刷新定时器元件与事件信号发生器集成，使得当检测到可能改变一个或多个存储器单元的数据保持时间的事件时，刷新定时器元件定义的刷新间隔被改变。在各种实施例中，放置一个或多个电路以监视整个存储器阵列，不同子阵列或不同子阵列的不同部分。这允许额外的刷新操作与实际事件紧密相关，从而提高整体效率。

8. 发明申请

WO2007126830A2 MEMORY ARRAY HAVING A PROGRAMMABLE WORD LENGTH, AND METHOD OF OPERATING SAME 审中-公开
标题翻译：具有可编程字长度的记忆阵列及其操作方法
公开(公告)号：WO2007126830A2
公开(公告)日：2007-11-08
申请号：PCT/US2007007591
申请日：2007-03-29
申请人： INNOVATIVE SILICON SA , CARMAN ERIC
发明人： CARMAN ERIC
IPC分类号： G11C16/04
CPC分类号： G11C7/1006 , G11C7/1048 , G11C11/404 , G11C11/4087 , G11C11/4093 , G11C2211/4016 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10879 , H01L27/1203 , H01L29/7841 , H01L29/785
摘要： A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array. In one aspect, write and/or read operations may be performed with respect to selected memory cells of a selected row of the memory array, while unselected memory cells of the selected row are undisturbed.
摘要翻译：具有存储单元阵列的存储单元阵列和器件（即集成电路器件，例如逻辑器件（例如，微控制器或微处理器）或存储器件（例如，分立存储器））包括电浮置其中电荷存储在晶体管的主体中的体晶体管，以及用于读取，控制和/或操作这样的存储单元阵列和这种器件的技术。存储单元阵列和器件包括可变和/或可编程的字长。字长涉及所选择的一行存储器单元的选定存储单元（其通过地址数据确定）。在一个实施例中，字长可以是所选行的任何数量的存储器单元，其小于或等于存储器阵列的所选行的存储器单元的总数。在一个方面，可以针对存储器阵列的选定行的所选择的存储器单元执行写入和/或读取操作，同时所选行的未选择的存储器单元不受干扰。

9. 发明申请

WO2007098044A2 MULTI-BIT MEMORY CELL HAVING ELECTRICALLY FLOATING BODY TRANSISTOR, AND METHOD OF PROGRAMMING AND READING SAME 审中-公开
标题翻译：具有电浮动体晶体管的多位存储单元以及编程和读取相同的方法
公开(公告)号：WO2007098044A2
公开(公告)日：2007-08-30
申请号：PCT/US2007/004163
申请日：2007-02-15
申请人： INNOVATIVE SILICON S.A. , CARMAN, Eric , OKHONIN, Serguei , JONES, Mark-Eric
发明人： CARMAN, Eric , OKHONIN, Serguei , JONES, Mark-Eric
IPC分类号： G11C11/34
CPC分类号： H01L29/7841 , G11C7/1006 , G11C7/16 , G11C11/404 , G11C11/565 , G11C2211/4016
摘要： There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc.) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory).
摘要翻译：这里描述了许多发明以及这些发明的许多方面和实施例，例如用于读取，写入和/或操作多位存储器的多位存储器单元和电路以及技术（具有多个这种存储器单元的存储器单元阵列）具有一个或多个电浮置体晶体管，其中电荷被存储在电浮置体晶体管的体区中。多位存储器单元存储多于一个数据位（例如2,3,4,5,6等）和/或多于两个数据状态（例如，3,4,5,6等等）数据或逻辑状态值得注意的是，存储器单元阵列可以包括集成电路器件的一部分，例如逻辑器件（例如，微处理器）或存储器器件的一部分（例如，分立存储器）。

10. 发明申请

WO2004102625A2 SEMICONDUCTOR MEMORY CELLL, ARRAY, ARCHITECTURE AND DEVICE, AND METHOD OF OPERATING SAME 审中-公开
标题翻译：半导体存储器存储器，阵列，架构和器件及其操作方法
公开(公告)号：WO2004102625A2
公开(公告)日：2004-11-25
申请号：PCT/US2004/014363
申请日：2004-05-07
申请人： INNOVATIVE SILICON, INC. , ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL) , FERRANT, Richard , OKHONIN, Serguei , CARMAN, Eric , BRON, Michel
发明人： FERRANT, Richard , OKHONIN, Serguei , CARMAN, Eric , BRON, Michel
IPC分类号： H01L
CPC分类号： G11C16/28 , G11C11/404 , G11C2211/4013 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell includes two transistors which store complementary data states. That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary "0") and the other transistor of the memory cell stores a logic high (a binary "ll"). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell. That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及从该存储单元读取数据并将数据写入该存储单元的存储单元和技术。在这方面，在本发明的这个方面的一个实施例中，存储单元包括存储互补数据状态的两个晶体管。也就是说，双晶体管存储单元包括相对于第二晶体管保持互补状态的第一晶体管。这样，当被编程时，存储单元的一个晶体管存储逻辑低（二进制“0”），并且存储单元的另一晶体管存储逻辑高（二进制“ll”）。可以通过采样，感测测量和/或检测存储在互补存储器单元的每个晶体管中的逻辑状态的极性来读取和/或确定双晶体管互补存储单元的数据状态。也就是说，通过采样，感测测量和/或检测存储在两个晶体管中的信号（电流或电压）的差异来读取双晶体管互补存储单元。

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