专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2012064912A2 BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION 审中-公开
标题翻译：所谓的SOI结隔离结构和装置以及制造方法
公开(公告)号：WO2012064912A2
公开(公告)日：2012-05-18
申请号：PCT/US2011060084
申请日：2011-11-10
申请人： IBM , JOHNSON JEFFREY B , NARASIMHA SHREESH , NAYFEH HASAN M , ONTALUS VIOREL C , ROBINSON ROBERT R
发明人： JOHNSON JEFFREY B , NARASIMHA SHREESH , NAYFEH HASAN M , ONTALUS VIOREL C , ROBINSON ROBERT R
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7824 , H01L21/76237 , H01L21/84 , H01L27/1203
摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer (105; Fig. 5) on a buried oxide (BOX) layer (115) of a silicon-on-insulator substrate (100); a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer (160, 165, and 170), a doped region (155) in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer (160), doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer (165), doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
摘要翻译：一种结构，一种FET，一种制造该结构和制造该FET的方法。所述结构包括：在绝缘体上硅衬底（100）上的掩埋氧化物（BOX）层（115）上的硅层（105;图5）; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层（160,165和170），所述硅层中的掺杂区域（155）和邻接 BOX层和沟槽的底部，掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层（160）; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层（165）; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。

2. 发明申请

WO2006113061A2 A HYBRID BULK-SOI 6T-SRAM CELL FOR IMPROVED CELL STABILITY AND PERFORMANCE 审中-公开
标题翻译：用于改善细胞稳定性和性能的混合体积6L-SRAM细胞
公开(公告)号：WO2006113061A2
公开(公告)日：2006-10-26
申请号：PCT/US2006011167
申请日：2006-03-27
申请人： IBM , CHANG LELAND , NARASIMHA SHREESH , ROHRER NORMAN J , SLEIGHT JEFFREY W
发明人： CHANG LELAND , NARASIMHA SHREESH , ROHRER NORMAN J , SLEIGHT JEFFREY W
IPC分类号： H01L29/94
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1203 , H01L27/1207
摘要： The present invention provides a 6T-SRAM semiconductintg structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk Si-region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has a silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.
摘要翻译：本发明提供了一种包括具有SOI区域和体硅区域的衬底的6T-SRAM半导体结构，其中SOI区域和体硅区域具有相同或不同的晶体取向; 将SOI区域与本体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层的顶部具有硅层。体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。阱接触还用于控制体Si区域中的FET的阈值电压，以优化由SOI和体Si区域FET的组合构建的SRAM单元的功率和性能。

3. 发明申请

WO2011043870A3 SPLIT LEVEL SHALLOW TRENCH ISOLATION FOR AREA EFFICIENT BODY CONTACTS IN SOI MOSFETS 审中-公开
标题翻译： SOI MOSFET的高分辨率高分辨率分析
公开(公告)号：WO2011043870A3
公开(公告)日：2011-06-23
申请号：PCT/US2010046567
申请日：2010-08-25
申请人： IBM , LI YING , NARASIMHA SHREESH , RAUSCH WERNER A
发明人： LI YING , NARASIMHA SHREESH , RAUSCH WERNER A
IPC分类号： H01L29/78 , H01L21/336 , H01L21/762
CPC分类号： H01L29/78615 , H01L21/74 , H01L21/76229 , H01L21/76283 , H01L29/66772
摘要： Disclosed is an SOI device on a bulk silicon layer which has an FET region, a body contact region and an STI region. The FET region is made of an SOI layer and an overlying gate. The STI region includes a first STI layer separating the SOI device from an adjacent SOI device. The body contact region includes an extension of the SOI layer, a second STI layer on the extension and a body contact in contact with the extension. The first and second STI layers are contiguous and of different thicknesses so as to form a split level STI.
摘要翻译：公开了具有FET区域，体接触区域和STI区域的体硅层上的SOI器件。 FET区域由SOI层和上覆栅极构成。 STI区域包括将SOI器件与相邻SOI器件分开的第一STI层。身体接触区域包括SOI层的延伸部，延伸部上的第二STI层和与延伸部接触的身体接触部。第一和第二STI层是连续的和不同的厚度，以便形成分级STI。

4. 发明申请

WO2006063060A3 DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS 审中-公开
标题翻译：具有增强应力状态的装置及相关方法
公开(公告)号：WO2006063060A3
公开(公告)日：2006-11-16
申请号：PCT/US2005044281
申请日：2005-12-08
申请人： IBM , CHIDAMBARRAO DURESETI , LI YING , MALIK RAJEEV , NARASIMHA SHREESH , YANG HAINING , ZHU HUILONG
发明人： CHIDAMBARRAO DURESETI , LI YING , MALIK RAJEEV , NARASIMHA SHREESH , YANG HAINING , ZHU HUILONG
IPC分类号： H01L21/31 , H01L23/58
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/66772 , Y10S438/938
摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.
摘要翻译：本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET（300）提供增加的横向应力状态以及用于制造这种器件的方法。本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫（360）施加到器件上，并施加与快速氮化硅衬垫相邻的第二氮化硅衬垫（370），其中所述第一和第二氮化硅衬垫中的至少一个在所述第一和第二氮化硅衬垫中的至少一个下方的硅沟道（330）中引起横向应力。

5. 发明公开

EP1834350A4 DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS 有权
标题翻译：具有延长曝光条件和相关程序DEVICE
公开(公告)号：EP1834350A4
公开(公告)日：2009-06-17
申请号：EP05853245
申请日：2005-12-08
申请人： IBM
发明人： CHIDAMBARRAO DURESETI , LI YING , MALIK RAJEEV , NARASIMHA SHREESH , YANG HAINING , ZHU HUILONG
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/66772 , Y10S438/938
摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.

6. 发明公开

EP1875516A4 A HYBRID BULK-SOI 6T-SRAM CELL FOR IMPROVED CELL STABILITY AND PERFORMANCE 审中-公开
标题翻译： HYBRIDE BULK-SOI-6T-SRAM-ZELLEFÜRVERBESSERTEZELLENSTABILITÄTUND-LEISTUNGSFÄHIGKEIT
公开(公告)号：EP1875516A4
公开(公告)日：2008-08-13
申请号：EP06739771
申请日：2006-03-27
申请人： IBM
发明人： CHANG LELAND , NARASIMHA SHREESH , ROHRER NORMAN J , SLEIGHT JEFFREY W
IPC分类号： H01L21/8244 , G11C11/412 , H01L21/84 , H01L27/11 , H01L27/12
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1203 , H01L27/1207
摘要： The present invention provides a 6T-SRAM semiconductintg structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk Si-region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has a silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.
摘要翻译：本发明提供了一种6T-SRAM半导体结构，其包括具有SOI区和体硅区的衬底，其中SOI区和体硅区具有相同或不同的结晶取向; 隔离SOI区域与体硅区域的隔离区域; 以及位于所述SOI区域中的至少一个第一器件和位于所述体硅区域中的至少一个第二器件。 SOI区域在绝缘层顶上具有硅层。体硅区还包括位于第二器件下方的阱区和与阱区的接触，其中接触稳定了浮体效应。阱接触也用于控制体硅区域中的FET的阈值电压，以优化由SOI和体硅区域FET的组合构建的SRAM单元的功率和性能。

7. 发明公开

EP2409332A4 GATED DIODE STRUCTURE AND METHOD INCLUDING RELAXED LINER 审中-公开
标题翻译：门控二极管的构造和松散涂层的方法
公开(公告)号：EP2409332A4
公开(公告)日：2012-01-25
申请号：EP10753837
申请日：2010-02-11
申请人： IBM
发明人： CHOU ANTHONY I , FREEMAN GREGORY G , MCSTAY KEVIN , NARASIMHA SHREESH
IPC分类号： H01L29/739 , H01L21/285 , H01L21/329 , H01L21/33 , H01L21/768 , H01L27/12
CPC分类号： H01L21/28518 , H01L21/76829 , H01L29/66356 , H01L29/7391

8. 发明专利

JP2010004006A Method and structure for soi body contact fet with reduced parasitic capacitance 审中-公开
标题翻译：具有降低PARASITIC电容的SOI体接触FET的方法和结构
公开(公告)号：JP2010004006A
公开(公告)日：2010-01-07
申请号：JP2008259405
申请日：2008-10-06
申请人： Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人： CHANG LELAND , CHOU ANTHONY I , NARASIMHA SHREESH , SLEIGHT JEFFREY W
IPC分类号： H01L29/786
CPC分类号： H01L29/78615 , H01L29/665 , H01L29/66772 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To reduce the parasitic capacitance of an semiconductor-on-insulator device by providing the semiconductor-on-insulator device with a body contact. SOLUTION: In one embodiment, the invention provides a semiconductor device that includes: a substrate including a semiconductor layer positioned overlaying an insulating layer, the semiconducting layer including a semiconducting body and isolation regions present around a perimeter of the semiconducting body; a gate structure overlaying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过提供绝缘体上半导体器件与体接触来减小绝缘体上半导体器件的寄生电容。解决方案：在一个实施例中，本发明提供了一种半导体器件，其包括：衬底，其包括覆盖绝缘层的半导体层，所述半导体层包括半导体本体和围绕半导体本体的周边存在的隔离区; 覆盖所述衬底的半导体层的栅极结构，所述栅极结构存在于所述半导体本体的上表面上的第一部分上; 以及通过非硅化物半导体区域与半导电体的第一部分分离的与半导体的第二部分直接物理接触的硅化物体接触。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2005094006A Method improving quality of defective semiconductor material 有权
标题翻译：改善缺陷半导体材料质量的方法
公开(公告)号：JP2005094006A
公开(公告)日：2005-04-07
申请号：JP2004266302
申请日：2004-09-14
申请人： Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人： BEDELL STEPHEN W , FOGEL KEITH E , NARASIMHA SHREESH
IPC分类号： H01L21/02 , H01L21/20 , H01L21/265 , H01L27/12
CPC分类号： H01L21/2022 , Y10S438/933
摘要： PROBLEM TO BE SOLVED: To provide an improving method of the quality of a defective semiconductor crystal in the vicinity of the surface thereof.
SOLUTION: A method where amorphization step and subsequent thermal treatment step are executed on the defective semiconductor crystal material is provided. In the amorphization step, a region including the surface area of the defective semiconductor crystal material is partially or completely amorphized. Next, the thermal treatment step is executed to recrystallize the amorphized area of the defective semiconductor crystal material. Recrystallization is achieved, by re-growing the solid phase crystal from the amorphized area of the defective semiconductor crystal material.
COPYRIGHT: (C)2005,JPO&NCIPI

10. 发明专利

JP2005317980A New material for contact etching layer that enhances device performance 有权
标题翻译：用于接触蚀刻层的新材料，增强器件性能
公开(公告)号：JP2005317980A
公开(公告)日：2005-11-10
申请号：JP2005131468
申请日：2005-04-28
申请人： Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人： ASHIMA B CHAKRAVARTI , NARASIMHA SHREESH , CHAN VICTOR , JUDSON HOLT , SATYA N CHAKRAVARTI
IPC分类号： H01L21/768 , C23C16/34 , H01L21/318 , H01L21/469 , H01L29/78
CPC分类号： H01L29/7843 , C23C16/345 , H01L21/3185
摘要： PROBLEM TO BE SOLVED: To provide a material that can exhibit a desirable stress in using a field effect transistor, e.g., sufficiently high stress for an etching stop liner (e.g., a stress that exceeds +10G dyne/cm
2 , stress of approximately +14.5G dyne/cm
2 in a preferred embodiment), and further continues to exhibit the desirable high stress after repeated annealing.
SOLUTION: Stress level of a nitride film is adjusted as two or more functions of the following: (1) selection of a starting material precursor to be used to make the nitride film, by use of which the starting material precursor is processed, (2) selection of a precursor including nitrogen, (3) the ratio of the starting material precursor and the precursor including nitrogen, (4) a set of CVD conditions for growing the film and (5) a thickness that grows the film. A rapid thermal chemical vapor deposition (RTCVD) film produced by reacting a compound including silicon, nitrogen and carbon (e.g., bis-t-butylaminosilane (BTBAS)) with NH
3 can provide an advantageous characteristic such as performance excellent in high use or an etching stop application. An ammonia treated BTBAS film is especially excellent in providing a high-stress characteristic and is capable of maintaining the high-stress characteristic even if annealing is repeated.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供在使用场效应晶体管时可以表现出期望的应力的材料，例如用于蚀刻停止衬垫的足够高的应力（例如，超过+ 10G达因/ cm 2的应力< 2 ，在优选实施例中约为+ 14.5G达因/厘米2 / SP>的应力），并且在反复退火之后还继续表现出期望的高应力。解决方案：将氮化膜的应力水平调整为以下两个或更多个功能：（1）选择用于制造氮化物膜的起始材料前体，通过使用原料前体进行处理，（2）包括氮的前体的选择，（3）原料前体和前体的比例包括氮的比例，（4）用于生长膜的一组CVD条件和（5）使膜生长的厚度。通过使包含硅，氮和碳的化合物（例如，双 - 叔丁基氨基硅烷（BTBAS））与NH 3 SBB反应生成的快速热化学气相沉积（RTCVD）膜可以提供有利的特性，例如性能优异的高使用或蚀刻停止应用。氨处理的BTBAS膜在提供高应力特性方面特别优异，并且即使重复退火也能够保持高应力特性。版权所有（C）2006，JPO＆NCIPI

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式