专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP1226501A4 NETWORK SWITCH AND COMPONENTS AND METHOD OF OPERATION 有权
标题翻译：网络交换机和部件工作程序
公开(公告)号：EP1226501A4
公开(公告)日：2003-10-01
申请号：EP00959158
申请日：2000-08-24
申请人： IBM
发明人： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , GALLO ANTHONY MATTEO , HEDDES MARCO C , RAO SRIDHAR , SIEGEL MICHAEL STEVEN , YOUNGMAN BRIAN ALAN , VERPLANKEN FABRICE JEAN
IPC分类号： G06F15/16 , G06F13/40 , G06F15/177 , H04L12/56 , G06F13/00 , G06F13/38 , G06F15/00 , G06F15/173 , G06F15/76
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

2. 发明申请

WO02087156A3 METHOD AND DEVICE FOR MULTICAST TRANSMISSIONS 审中-公开
标题翻译：用于多播传输的方法和装置
公开(公告)号：WO02087156A3
公开(公告)日：2002-12-19
申请号：PCT/GB0200383
申请日：2002-01-28
申请人： IBM , IBM UK
发明人： BASSO CLAUDE , CALVIGNAC JEAN LOUIS , HEDDES MARCO , LOGAN JOSEPH FRANKLIN , VERPLANKEN FABRICE JEAN
IPC分类号： H04L12/18 , H04L12/56
CPC分类号： H04L49/901 , H04L12/1881 , H04L47/10 , H04L47/20 , H04L49/90
摘要： Multicast transmission on network processors is disclosed in order both to minimize multicast transmission memory requirements and to account for port performance discrepancies. Frame data for multicast transmission on a network processor is read into buffers to which are associated various control structures and a reference frame. The reference frame and the associated control structures permit multicast targets to be serviced without creating multiple copies of the frame. Furthermore this same reference frame and control structures allow buffers allocated for each multicast target to be returned to the free buffer queue without waiting until all multicast transmissions are complete.
摘要翻译：公开了网络处理器上的组播传输，以便最小化多播传输存储器要求并考虑到端口性能差异。将网络处理器上的组播传输的帧数据读入与各种控制结构和参考帧相关联的缓冲器。参考帧和相关联的控制结构允许在不创建帧的多个拷贝的情况下对多播目标进行服务。此外，相同的参考帧和控制结构允许为每个多播目标分配的缓冲区返回到空闲缓冲器队列，而不等待所有多播传输完成。

3. 发明申请

WO02069563A3 NETWORK ADAPTER 审中-公开
标题翻译：网络适配器
公开(公告)号：WO02069563A3
公开(公告)日：2003-04-17
申请号：PCT/GB0200748
申请日：2002-02-20
申请人： IBM , IBM UK
发明人： CALVIGNAC JEAN LOUIS , HEDDES MARCO , LOGAN JOSEPH FRANKLIN , VERPLANKEN FABRICE JEAN
IPC分类号： H04L12/861 , H04L29/06
CPC分类号： H04L49/90 , H04L47/50 , H04L49/901
摘要： A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.
摘要翻译：一种用于减少对存储器的访问次数以在帧控制块中获得所需字段信息的方法和系统。在本发明的一个实施例中，系统包括被配置为处理数据帧的处理器。处理器可以包括被配置为接收和发送数据帧的数据流单元，其中每个数据帧可以具有相关联的帧控制块。每个帧控制块包括第一和第二控制块。处理器还可以包括耦合到数据流单元的第一存储器，其被配置为存储用于第一控制块的字段信息。处理器还可以包括与数据流单元耦合的调度器，其中调度器被配置为调度由数据流单元接收的数据帧。调度器可以包括被配置为存储第二控制块的字段信息的第二存储器。

4. 发明申请

WO02069601A2 LINKING FRAME DATA BY INSERTING QUALIFIERS IN CONTROL BLOCKS 审中-公开
标题翻译：通过在控制块中插入合格者来连接框架数据
公开(公告)号：WO02069601A2
公开(公告)日：2002-09-06
申请号：PCT/GB0200751
申请日：2002-02-20
申请人： IBM , IBM UK
发明人： CALVIGNAC JEAN LOUIS , HEDDES MARCO , LOGAN JOSEPH FRANKLIN , VERPLANKEN FABRICE JEAN
IPC分类号： H04L12/861 , G06F13/42 , H04L12/741 , H04L29/06
CPC分类号： H04L49/3081 , G06F13/4243 , H04L2012/5681
摘要： A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.
摘要翻译：一种通过在控制块中插入限定符来减少存储器访问的方法和系统。在一个实施例中，系统包括被配置为处理数据帧的处理器。处理器可以包括多个缓冲器，其被配置为存储数据帧，其中每个数据帧可以与帧控制块相关联。与数据帧相关联的每个帧控制块可以与一个或多个缓冲器控制块相关联。每个控制块，例如帧控制块，缓冲器控制块，可以包括包含与当前控制块无关的信息的一个或多个限定符字段。相反，限定符可以包括与另一个控制块有关的信息。队列中的最后帧控制块以及与帧控制块相关联的最后一个缓冲器控制块可以包括没有信息的字段，从而减少对这些字段中的访问信息的存储器访问。

5. 发明申请

WO0179992A3 METHOD AND SYSTEM FOR SCHEDULING INFORMATION USING CALENDARS 审中-公开
标题翻译：使用日历安排信息的方法和系统
公开(公告)号：WO0179992A3
公开(公告)日：2002-02-21
申请号：PCT/GB0101337
申请日：2001-03-26
申请人： IBM , IBM UK
发明人： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , HEDDES MARCO , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
IPC分类号： H04L12/54 , H04L12/70 , H04L12/851 , H04L12/873 , H04L12/875 , H04Q11/04 , H04L12/56
CPC分类号： H04L12/5601 , H04L47/2408 , H04L47/50 , H04L47/527 , H04L47/564 , H04L2012/5636 , H04L2012/5649 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681
摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.
摘要翻译：一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。优选实施例中的优先级包括低延迟服务，最小带宽，加权公平排队以及用于在较长时间内防止用户继续超过其服务水平的系统。本发明包括具有不同服务速率的多个日历，以允许用户选择他所期望的服务速率。如果客户选择了高带宽进行服务，则客户将被包含在比客户选择较低带宽的情况下更常服务的日历。

6. 发明公开

EP1208676A4 NETWORK SWITCH USING NETWORK PROCESSOR AND METHODS 有权
标题翻译：与使用网络处理器和方法，电源开关
公开(公告)号：EP1208676A4
公开(公告)日：2008-02-27
申请号：EP00959159
申请日：2000-08-24
申请人： IBM
发明人： ALLEN JAMES JR , BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , GAUR SANTOSH PRASAD , HEDDES MARCO C , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
IPC分类号： G06F15/16 , G06F15/177 , H04L12/56 , H04Q3/00 , H04Q3/545 , H04J3/24 , H04Q11/04
CPC分类号： H04Q3/002 , H04L45/742 , H04L49/254 , H04L49/351 , H04L49/354 , H04L49/602 , H04L2212/00 , H04Q3/5455 , H04Q2213/1302 , H04Q2213/13034 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/13104 , H04Q2213/13106 , H04Q2213/13107 , H04Q2213/13322
摘要： A network switching apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors (12) and a suite of peripheral elements formed on a semiconductor substrate (10). The interface processors (12) and peripherals together form a network processor capable of cooperating with other elements including an optional switch fabric device in executing instructions directing the flow of data in the network.

7. 发明公开

EP1222517A4 VLSI NETWORK PROCESSOR AND METHODS 审中-公开
标题翻译： VLSI网络处理器和方法
公开(公告)号：EP1222517A4
公开(公告)日：2007-03-21
申请号：EP00957270
申请日：2000-08-24
申请人： IBM
发明人： BARKER KENNETH JAMES , BASS BRIAN MITCHELL , CALVIGNAC JEAN-LOUIS , HEDDES MARCO C , SIEGEL MICHAEL STEVEN , TROMBLEY MICHAEL RAYMOND , VERPLANKEN FABRICE JEAN
IPC分类号： H04L29/06 , H04L12/56
CPC分类号： H04L29/06 , H04L49/1507 , H04L49/45 , H04L69/12
摘要： A network processor (10) useful in network switch apparatus and methods of operating such a processor (10) in which data flow handling and flexibility is enhanced by the cooperation of a plurality of interface processors (16, 34) formed on a semiconductor substrate. The interface processors (16, 34) provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate.

8. 发明公开

EP1226509A4 NETWORK PROCESSOR PROCESSING COMPLEX AND METHODS 审中-公开
标题翻译：网络处理器处理复杂和方法
公开(公告)号：EP1226509A4
公开(公告)日：2007-09-26
申请号：EP00957269
申请日：2000-08-24
申请人： IBM
发明人： BASS BRIAN MITCHELL , CALVIGNAC JEAN-LOUIS , GALLO ANTHONY MATTEO , HEDDES MARCO C , LEAVENS ROSS BOYD , PATEL PIYUSH CHUNILAL , RINALDI MARK ANTHONY , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
IPC分类号： G06F15/16 , G06F15/80 , H04L12/56 , G06F15/00
CPC分类号： H04L49/602 , G06F15/80 , H04L49/351
摘要： A network processor (10) useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of an embedded processor complex (12) with a suite of peripherals (14-36 and 40), all formed on a common semiconductor substrate. The interface processors (16, 34) provide data path for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate, while storage of transiting data flow portions is provided by memory peripherals and interfaces to external memory elements.

9. 发明公开

EP1208447A4 NETWORK PROCESSOR, MEMORY ORGANIZATION AND METHODS 有权
标题翻译：网络处理器，存储器构成和程序
公开(公告)号：EP1208447A4
公开(公告)日：2004-10-20
申请号：EP00959157
申请日：2000-08-24
申请人： IBM
发明人： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , HEDDES MARCO C , PATEL PIYUSH CHUNILAL , REVILLA JUAN GUILLERMO , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
IPC分类号： G06F15/167 , G06F12/06 , G06F15/177 , H04L12/56 , H04Q11/04 , G06F15/16 , G06F12/00 , G06F13/16
CPC分类号： H04Q11/0478 , H04L2012/5681
摘要： A network switch apparatus (10), components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate (10). The memory elements and interface processors together form a network processor (10) capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by a plurality of processors.

10. 发明专利

JP2001222505A QUEUE MANAGER FOR BUFFER 失效
公开(公告)号：JP2001222505A
公开(公告)日：2001-08-17
申请号：JP2000384352
申请日：2000-12-18
申请人： IBM
发明人： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , HEDDES MARCO C , SIEGEL MICHAEL STEVEN , MICHAEL RAYMOND TROMBLAY , VERPLANKEN FABRICE JEAN
IPC分类号： G06F12/00 , G06F5/06 , G06F5/14 , G06F12/02 , G06F12/08 , G06F13/00 , G06F13/14 , G06F13/16 , G06F13/38
摘要： PROBLEM TO BE SOLVED: To provide a bandwidth maintenance queue manager for (first-in first-out)FIFO buffer provided with another DRAM storage device for maintaining a FIFO queue. SOLUTION: A FIFO buffer is used on an ASIC chip so that plural queue entries can be stored and retrieved. As long as the total size of queues does not exceed a usable storage device in the buffer, any data storage device is not required more. When supplied data exceeds the buffer storage space of a certain prescribed quantity in the FIFO buffer, however, these data are written in the other data storage device in the form of packet and read from that storage device. That packet has an optimal size for maintaining the peak performance of the data storage device and is written in the data storage device in a way such as queuing with the address sequence of FIFO.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式