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1. 发明申请

US20070161230A1 UV curing of low-k porous dielectrics 有权
标题翻译：低k多孔电介质的UV固化
公开(公告)号：US20070161230A1
公开(公告)日：2007-07-12
申请号：US11328596
申请日：2006-01-10
申请人： I-I Chen , Tien-I Bao , Shwang-Ming Cheng , Chen-Hua Yu
发明人： I-I Chen , Tien-I Bao , Shwang-Ming Cheng , Chen-Hua Yu
IPC分类号： H01L21/4763 , H01L21/469
CPC分类号： H01L21/76826 , H01L21/7682 , H01L21/76825 , H01L2221/1047
摘要： A method of manufacturing a semiconductor device having a low-k dielectric layer is provided. An embodiment comprises forming a dielectric layer on a substrate, wherein the layer comprises a pore generating material dispersed in an uncured matrix. A second step comprises forming pores in the uncured matrix by irradiating the layer with radiation having a first wavelength. After pore forming, a third step comprises cross-linking the dielectric by irradiating it at a second wavelength, the second being less than the first. In an embodiment, the irradiating wavelengths comprise ultra-violet radiation. Embodiments may further include repairing processing damage wherein the damage includes dangling bonds or silanol formation. The repairing includes annealing in a carbon-containing ambient such as C2H4, C3H6, or hexamethyldisilazane (HMDS).
摘要翻译：提供一种制造具有低k电介质层的半导体器件的方法。一个实施方案包括在基底上形成介电层，其中该层包含分散在未固化的基质中的孔产生材料。第二步骤包括通过用具有第一波长的辐射照射该层来在未固化的基质中形成孔。在成孔之后，第三步骤包括通过以第二波长照射电介质来交联电介质，第二步小于第一波长。在一个实施例中，照射波长包括紫外辐射。实施方案可以进一步包括修复处理损伤，其中损伤包括悬挂键或硅烷醇形成。修复包括在含碳环境中退火，例如C 2 H 4 H 3，C 3 H 6，或六甲基二硅氮烷（HMDS）。

2. 发明申请

US20070202676A1 Integration scheme for cu/low-k interconnects 有权
标题翻译： cu / low-k互连的集成方案
公开(公告)号：US20070202676A1
公开(公告)日：2007-08-30
申请号：US11361331
申请日：2006-02-24
申请人： Ming Yeh , Chen-Hua Yu , Keng-Chu Lin , Tien-I Bao , Shwang-Ming Cheng
发明人： Ming Yeh , Chen-Hua Yu , Keng-Chu Lin , Tien-I Bao , Shwang-Ming Cheng
IPC分类号： H01L21/44
CPC分类号： H01L21/76834 , H01L21/02063 , H01L21/02126 , H01L21/02271 , H01L21/02304 , H01L21/02362 , H01L21/31633 , H01L21/31695 , H01L21/76808 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L21/76846
摘要： A semiconductor structure having an opening formed in a porous dielectric layer is provided. The exposed pores of the dielectric layer along the sidewalls of the opening are sealed. The sealing may comprise a selective or a non-selective deposition method. The sealing layer has a substantially uniform thickness in one portion of the opening and a non-uniform thickness in another portion of the opening. A damascene interconnect structure having a pore sealing layer is provided as is its method of manufacture.
摘要翻译：提供了一种形成在多孔电介质层中的开口的半导体结构。沿着开口的侧壁的电介质层的暴露的孔被密封。密封可以包括选择性或非选择性沉积方法。密封层在开口的一部分中具有基本均匀的厚度，并且在开口的另一部分中具有不均匀的厚度。如其制造方法那样提供具有孔密封层的镶嵌互连结构。

3. 发明授权

US07564136B2 Integration scheme for Cu/low-k interconnects 有权
标题翻译： Cu / low-k互连的集成方案
公开(公告)号：US07564136B2
公开(公告)日：2009-07-21
申请号：US11361331
申请日：2006-02-24
申请人： Ming Ling Yeh , Chen-Hua Yu , Keng-Chu Lin , Tien-I Bao , Shwang-Ming Cheng
发明人： Ming Ling Yeh , Chen-Hua Yu , Keng-Chu Lin , Tien-I Bao , Shwang-Ming Cheng
IPC分类号： H01L23/48
CPC分类号： H01L21/76834 , H01L21/02063 , H01L21/02126 , H01L21/02271 , H01L21/02304 , H01L21/02362 , H01L21/31633 , H01L21/31695 , H01L21/76808 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L21/76846
摘要： A semiconductor structure having an opening formed in a porous dielectric layer is provided. The exposed pores of the dielectric layer along the sidewalls of the opening are sealed. The sealing may comprise a selective or a non-selective deposition method. The sealing layer has a substantially uniform thickness in one portion of the opening and a non-uniform thickness in another portion of the opening. A damascene interconnect structure having a pore sealing layer is provided as is its method of manufacture.
摘要翻译：提供了一种形成在多孔电介质层中的开口的半导体结构。沿着开口的侧壁的电介质层的暴露的孔被密封。密封可以包括选择性或非选择性沉积方法。密封层在开口的一部分中具有基本均匀的厚度，并且在开口的另一部分中具有不均匀的厚度。如其制造方法那样提供具有孔密封层的镶嵌互连结构。

4. 发明授权

US07314828B2 Repairing method for low-k dielectric materials 有权
标题翻译：低k电介质材料的修复方法
公开(公告)号：US07314828B2
公开(公告)日：2008-01-01
申请号：US11184589
申请日：2005-07-19
申请人： Keng-Chu Lin , Chen-Hua Yu , Ching-Ya Wang , Chia-Cheng Chou , Tien-I Bao , Shwang-Ming Cheng
发明人： Keng-Chu Lin , Chen-Hua Yu , Ching-Ya Wang , Chia-Cheng Chou , Tien-I Bao , Shwang-Ming Cheng
IPC分类号： H01L21/4763
CPC分类号： H01L21/02211 , H01L21/0206 , H01L21/02074 , H01L21/02101 , H01L21/02126 , H01L21/02203 , H01L21/02334 , H01L21/02337 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/3105 , H01L21/31058 , H01L21/312 , H01L21/3122 , H01L21/31629 , H01L21/76801 , H01L21/76814 , H01L21/76825 , H01L21/76834
摘要： A method of forming a low-k dielectric layer and forming a structure in the low-k dielectric layer includes depositing a low-k dielectric layer over a substrate, performing a first treatment to the low-k dielectric layer, performing post-formation processes, and performing a second treatment to the low-k dielectric layer. The k value of the low-k dielectric layer is lowered by the first treatment. The post-formation processes performed to the low-k dielectric layer include at least one low-k dielectric material damaging process. The second treatment restores the low-k dielectric layer. Preferably, each of the first and second treatments includes a curing process selected from e-beam curing, ultraviolet curing, plasma curing, SCCO2 cleaning, and combinations thereof.
摘要翻译：形成低k电介质层并在低k电介质层中形成结构的方法包括在衬底上沉积低k电介质层，对低k电介质层进行第一次处理，执行后形成工艺，并对低k电介质层进行第二处理。通过第一次处理，低k电介质层的k值降低。对低k电介质层进行的后期处理包括至少一个低k电介质材料破坏过程。第二种处理恢复了低k电介质层。优选地，第一和第二处理中的每一个包括选自电子束固化，紫外线固化，等离子体固化，SCCO 2清洁及其组合的固化过程。

5. 发明申请

US20070020952A1 Repairing method for low-k dielectric materials 有权
标题翻译：低k电介质材料的修复方法
公开(公告)号：US20070020952A1
公开(公告)日：2007-01-25
申请号：US11184589
申请日：2005-07-19
申请人： Keng-Chu Lin , Chen-Hua Yu , Ching-Ya Wang , Chia-Cheng Chou , Tien-I Bao , Shwang-Ming Cheng
发明人： Keng-Chu Lin , Chen-Hua Yu , Ching-Ya Wang , Chia-Cheng Chou , Tien-I Bao , Shwang-Ming Cheng
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02211 , H01L21/0206 , H01L21/02074 , H01L21/02101 , H01L21/02126 , H01L21/02203 , H01L21/02334 , H01L21/02337 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/3105 , H01L21/31058 , H01L21/312 , H01L21/3122 , H01L21/31629 , H01L21/76801 , H01L21/76814 , H01L21/76825 , H01L21/76834
摘要： A method of forming a low-k dielectric layer and forming a structure in the low-k dielectric layer includes depositing a low-k dielectric layer over a substrate, performing a first treatment to the low-k dielectric layer, performing post-formation processes, and performing a second treatment to the low-k dielectric layer. The k value of the low-k dielectric layer is lowered by the first treatment. The post-formation processes performed to the low-k dielectric layer include at least one low-k dielectric material damaging process. The second treatment restores the low-k dielectric layer. Preferably, each of the first and second treatments includes a curing process selected from e-beam curing, ultraviolet curing, plasma curing, SCCO2 cleaning, and combinations thereof.
摘要翻译：形成低k电介质层并在低k电介质层中形成结构的方法包括在衬底上沉积低k电介质层，对低k电介质层进行第一次处理，执行后形成工艺，并对低k电介质层进行第二处理。通过第一次处理，低k电介质层的k值降低。对低k电介质层进行的后期处理包括至少一个低k电介质材料破坏过程。第二种处理恢复了低k电介质层。优选地，第一和第二处理中的每一个包括选自电子束固化，紫外线固化，等离子体固化，SCCO 2清洁及其组合的固化过程。

6. 发明申请

US20060172531A1 Sealing pores of low-k dielectrics using CxHy 有权
标题翻译：使用CxHy密封低k电介质的孔隙
公开(公告)号：US20060172531A1
公开(公告)日：2006-08-03
申请号：US11048518
申请日：2005-02-01
申请人： Keng-Chu Lin , Shwang-Ming Cheng , Ming Yeh , Tien-I Bao
发明人： Keng-Chu Lin , Shwang-Ming Cheng , Ming Yeh , Tien-I Bao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831
摘要： A semiconductor method of manufacturing involving porous and/or carbon containing, low-k dielectrics is provided. The method includes forming a hydrocarbon of the general composition CxHy on the surface of the low-k dielectric. The hydrocarbon layer includes depositing a precursor material, preferably C2H4 or (CH3)2CHC6H6CH3. In accordance with embodiments of this invention, carbon diffuses into the low-k dielectric, thereby reducing carbon depletion damage caused by plasma processing or etching. Surface dielectric pores damaged by plasma processing are also repaired by sealing them with the CXHY layer. Embodiments include semiconductor devices, such as devices having damascene interconnect structures, manufacturing using methods provided.
摘要翻译：提供了涉及含有多孔和/或碳的低k电介质的半导体制造方法。该方法包括在低k电介质的表面上形成总体组成为C H 的烃。烃层包括沉积前体材料，优选C 2 H 4 H 3或（CH 3 CH 3）2 CH 3， 6> 6 6 3。根据本发明的实施例，碳扩散到低k电介质中，从而减少由等离子体处理或蚀刻引起的碳损耗损伤。通过等离子体处理损坏的表面电介质孔也通过用C H 层密封来修复。实施例包括半导体器件，例如具有镶嵌互连结构的器件，使用提供的方法的制造。

7. 发明授权

US07135402B2 Sealing pores of low-k dielectrics using CxHy 有权
标题翻译：使用CxHy密封低k电介质的孔隙
公开(公告)号：US07135402B2
公开(公告)日：2006-11-14
申请号：US11048518
申请日：2005-02-01
申请人： Keng-Chu Lin , Shwang-Ming Cheng , Ming Ling Yeh , Tien-I Bao
发明人： Keng-Chu Lin , Shwang-Ming Cheng , Ming Ling Yeh , Tien-I Bao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831
摘要： A semiconductor method of manufacturing involving porous and/or carbon containing, low-k dielectrics is provided. The method includes forming a hydrocarbon of the general composition CxHy on the surface of the low-k dielectric. The hydrocarbon layer includes depositing a precursor material, preferably C2H4 or (CH3)2CHC6H6CH3. In accordance with embodiments of this invention, carbon diffuses into the low-k dielectric, thereby reducing carbon depletion damage caused by plasma processing or etching. Surface dielectric pores damaged by plasma processing are also repaired by sealing them with the CxHy layer. Embodiments include semiconductor devices, such as devices having damascene interconnect structures, manufacturing using methods provided.
摘要翻译：提供了涉及含有多孔和/或碳的低k电介质的半导体制造方法。该方法包括在低k电介质的表面上形成总体组成为C H 的烃。烃层包括沉积前体材料，优选C 2 H 4 H 3或（CH 3 CH 3）2 CH 3， 6> 6 6 3。根据本发明的实施例，碳扩散到低k电介质中，从而减少由等离子体处理或蚀刻引起的碳损耗损伤。通过用等离子体处理损坏的表面电介质孔也通过用C x H H y层密封来修复。实施例包括半导体器件，例如具有镶嵌互连结构的器件，使用提供的方法的制造。

8. 发明申请

US20060172530A1 CxHy sacrificial layer for cu/low-k interconnects 有权
标题翻译： CxHy用于cu / low-k互连的牺牲层
公开(公告)号：US20060172530A1
公开(公告)日：2006-08-03
申请号：US11048215
申请日：2005-02-01
申请人： Shwang-Ming Cheng , Ming Yeh , Tien-I Bao , Keng-Chu Lin
发明人： Shwang-Ming Cheng , Ming Yeh , Tien-I Bao , Keng-Chu Lin
IPC分类号： H01L21/461 , H01L23/52
CPC分类号： H01L21/02274 , H01L21/02118 , H01L21/0212 , H01L21/02126 , H01L21/02129 , H01L21/02131 , H01L21/02134 , H01L21/02137 , H01L21/02203 , H01L21/312 , H01L21/76802 , H01L21/76807 , H01L21/76829 , H01L21/76831
摘要： A semiconductor method of manufacturing involving low-k dielectrics is provided. The method includes depositing a hydrocarbon of the general composition CxHy on the surface of a low-k dielectric. The hydrocarbon layer is deposited by reacting a precursor material, preferably C2H4 or (CH3)2CHC6H6CH3, using a PECVD process. In accordance with embodiments of this invention, carbon diffuses into the low-k dielectric, thereby reducing low-k dielectric damage caused by plasma processing or etching. Other embodiments comprise a semiconductor device having a low-k dielectric, wherein the low-k dielectric has carbon-adjusted dielectric region adjacent a trench sidewall and a bulk dielectric region. In preferred embodiments, the carbon-adjusted dielectric region has a carbon concentration not more than about 5% less than in the bulk dielectric region.
摘要翻译：提供涉及低k电介质的半导体制造方法。该方法包括在低k电介质的表面上沉积一般组合物C x H y Y y的烃。烃层通过使前体材料，优选C 2 H 4 H 3或（CH 3）3 H 2， CHC 6 6 H 3 CH 3，使用PECVD法。根据本发明的实施例，碳扩散到低k电介质中，由此降低由等离子体处理或蚀刻引起的低k电介质损伤。其他实施例包括具有低k电介质的半导体器件，其中低k电介质具有邻近沟槽侧壁和大块电介质区域的碳调节介电区域。在优选的实施方案中，碳调节的电介质区域的碳浓度比体电介质区域的碳浓度小约不超过约5％。

9. 发明授权

US07405481B2 Glue layer for adhesion improvement between conductive line and etch stop layer in an integrated circuit chip 有权
标题翻译：用于在集成电路芯片中的导电线和蚀刻停止层之间的粘附改善的胶层
公开(公告)号：US07405481B2
公开(公告)日：2008-07-29
申请号：US11004065
申请日：2004-12-03
申请人： Keng-Chu Lin , Yung-Cheng Lu , Shwang-Ming Cheng
发明人： Keng-Chu Lin , Yung-Cheng Lu , Shwang-Ming Cheng
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/76832 , H01L21/76834 , H01L2924/0002 , H01L2924/00
摘要： In an integrated circuit chip, a conductive line is formed in a first IMD layer. The conductive line is formed of a conductive line material that tends to form an oxide when exposed to an oxygen-containing substance. A glue layer is formed on the conductive line. The glue layer is formed of a non-oxygen-containing material capable of providing an oxygen barrier over the conductive line. The glue layer has a hardness greater than that of the conductive line. The glue layer preferably has a thickness between about 15 angstroms and about 75 angstroms. The etch stop layer is formed on the glue layer. The etch stop layer has a hardness greater than that of the glue layer. A second IMD layer is formed on the etch stop layer. The etch stop layer and/or the second IMD layer may be formed with a material comprising oxygen without oxidizing the conductive line.
摘要翻译：在集成电路芯片中，在第一IMD层中形成导线。导电线由暴露于含氧物质时易于形成氧化物的导电线材料形成。在导电线上形成胶层。胶层由能够在导电线上提供氧阻隔的非含氧材料形成。胶层的硬度大于导电线的硬度。胶层优选地具有在约15埃至约75埃之间的厚度。蚀刻停止层形成在胶层上。蚀刻停止层的硬度大于胶层的硬度。在蚀刻停止层上形成第二IMD层。蚀刻停止层和/或第二IMD层可以由包含氧的材料形成而不氧化导电线。

10. 发明申请

US20060118921A1 Glue layer for adhesion improvement between conductive line and etch stop layer in an integrated circuit chip 有权
标题翻译：用于在集成电路芯片中的导电线和蚀刻停止层之间的粘附改善的胶层
公开(公告)号：US20060118921A1
公开(公告)日：2006-06-08
申请号：US11004065
申请日：2004-12-03
申请人： Keng-Chu Lin , Yung-Cheng Lu , Shwang-Ming Cheng
发明人： Keng-Chu Lin , Yung-Cheng Lu , Shwang-Ming Cheng
IPC分类号： H01L23/58
CPC分类号： H01L21/76832 , H01L21/76834 , H01L2924/0002 , H01L2924/00
摘要： In an integrated circuit chip, a conductive line is formed in a first IMD layer. The conductive line is formed of a conductive line material that tends to form an oxide when exposed to an oxygen-containing substance. A glue layer is formed on the conductive line. The glue layer is formed of a non-oxygen-containing material capable of providing an oxygen barrier over the conductive line. The glue layer has a hardness greater than that of the conductive line. The glue layer preferably has a thickness between about 15 angstroms and about 75 angstroms. The etch stop layer is formed on the glue layer. The etch stop layer has a hardness greater than that of the glue layer. A second IMD layer is formed on the etch stop layer. The etch stop layer and/or the second IMD layer may be formed with a material comprising oxygen without oxidizing the conductive line.
摘要翻译：在集成电路芯片中，在第一IMD层中形成导线。导电线由暴露于含氧物质时易于形成氧化物的导电线材料形成。在导电线上形成胶层。胶层由能够在导电线上提供氧阻隔的非含氧材料形成。胶层的硬度大于导电线的硬度。胶层优选地具有在约15埃至约75埃之间的厚度。蚀刻停止层形成在胶层上。蚀刻停止层的硬度大于胶层的硬度。在蚀刻停止层上形成第二IMD层。蚀刻停止层和/或第二IMD层可以由包含氧的材料形成而不氧化导电线。

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