专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060181915A1 Phase change memory device providing compensation for leakage current 有权
标题翻译：提供漏电流补偿的相变存储器件
公开(公告)号：US20060181915A1
公开(公告)日：2006-08-17
申请号：US11319266
申请日：2005-12-29
申请人： Hyung-Rok Oh , Woo-Yeong Cho , Hye-Jin Kim
发明人： Hyung-Rok Oh , Woo-Yeong Cho , Hye-Jin Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C7/12 , G11C13/0004 , G11C13/0026 , G11C2213/79
摘要： A semiconductor memory device includes a plurality of phase change memory cells connected to the same bitline and different respective word lines. A read operation is performed on one of the memory cells by selecting the bitline and a corresponding wordline. While the read operation is performed, leakage current produced by non-selected memory cells is detected by a leakage detecting circuit and compensated by a leakage current supply circuit.
摘要翻译：半导体存储器件包括连接到同一位线和不同相应字线的多个相变存储器单元。通过选择位线和相应的字线，对存储器单元之一执行读取操作。在执行读取操作的同时，由漏电检测电路检测由未选择的存储单元产生的漏电流，并由泄漏电流供给电路进行补偿。

2. 发明申请

US20060092690A1 Magneto-resistive RAM having multi-bit cell array structure 有权
标题翻译：具有多位单元阵列结构的磁阻RAM
公开(公告)号：US20060092690A1
公开(公告)日：2006-05-04
申请号：US11260602
申请日：2005-10-27
申请人： Hye-Jin Kim , Woo-Yeong Cho , Hyung-Rok Oh
发明人： Hye-Jin Kim , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C11/00
CPC分类号： H03L7/0812 , B82Y10/00 , G11C11/15 , G11C11/16 , G11C11/5607 , G11C2211/5615 , H01L27/228 , H03L7/0891
摘要： A magnetic random access memory (RAM) with a multi-bit cell array structure includes an access transistor formed on a substrate, first through third resistance-variable elements, and first through third current supplying lines. The first through third resistance-variable elements are disposed between a bit line and the access transistor, and electrically connected to each other. The first through third current supplying lines are stacked alternately with the first through third resistance-variable elements. The first through third resistance-variable elements have equal resistances.
摘要翻译：具有多比特单元阵列结构的磁随机存取存储器（RAM）包括形成在基片上的存取晶体管，第一至第三电阻可变元件以及第一至第三电流线。第一至第三电阻可变元件设置在位线和存取晶体管之间，并且彼此电连接。第一至第三电流供应线与第一至第三电阻可变元件交替堆叠。第一至第三电阻可变元件具有相等的电阻。

3. 发明授权

US07463509B2 Magneto-resistive RAM having multi-bit cell array structure 有权
标题翻译：具有多位单元阵列结构的磁阻RAM
公开(公告)号：US07463509B2
公开(公告)日：2008-12-09
申请号：US11260602
申请日：2005-10-27
申请人： Hye-Jin Kim , Woo-Yeong Cho , Hyung-Rok Oh
发明人： Hye-Jin Kim , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C11/00
CPC分类号： H03L7/0812 , B82Y10/00 , G11C11/15 , G11C11/16 , G11C11/5607 , G11C2211/5615 , H01L27/228 , H03L7/0891
摘要： A magnetic random access memory (RAM) with a multi-bit cell array structure includes an access transistor formed on a substrate, first through third resistance-variable elements, and first through third current supplying lines. The first through third resistance-variable elements are disposed between a bit line and the access transistor, and electrically connected to each other. The first through third current supplying lines are stacked alternately with the first through third resistance-variable elements. The first through third resistance-variable elements have equal resistances.
摘要翻译：具有多比特单元阵列结构的磁随机存取存储器（RAM）包括形成在基片上的存取晶体管，第一至第三电阻可变元件以及第一至第三电流线。第一至第三电阻可变元件设置在位线和存取晶体管之间，并且彼此电连接。第一至第三电流供应线与第一至第三电阻可变元件交替堆叠。第一至第三电阻可变元件具有相等的电阻。

4. 发明授权

US07245526B2 Phase change memory device providing compensation for leakage current 有权
标题翻译：提供漏电流补偿的相变存储器件
公开(公告)号：US07245526B2
公开(公告)日：2007-07-17
申请号：US11319266
申请日：2005-12-29
申请人： Hyung-Rok Oh , Woo-Yeong Cho , Hye-Jin Kim
发明人： Hyung-Rok Oh , Woo-Yeong Cho , Hye-Jin Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C7/12 , G11C13/0004 , G11C13/0026 , G11C2213/79
摘要： A semiconductor memory device includes a plurality of phase change memory cells connected to the same bitline and different respective word lines. A read operation is performed on one of the memory cells by selecting the bitline and a corresponding wordline. While the read operation is performed, leakage current produced by non-selected memory cells is detected by a leakage detecting circuit and compensated by a leakage current supply circuit.
摘要翻译：半导体存储器件包括连接到同一位线和不同相应字线的多个相变存储器单元。通过选择位线和相应的字线，对存储器单元之一执行读取操作。在执行读取操作的同时，由漏电检测电路检测由未选择的存储单元产生的漏电流，并由泄漏电流供给电路进行补偿。

5. 发明授权

US07710767B2 Memory cell array biasing method and a semiconductor memory device 有权
标题翻译：存储单元阵列偏置方法和半导体存储器件
公开(公告)号：US07710767B2
公开(公告)日：2010-05-04
申请号：US11969326
申请日：2008-01-04
申请人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
摘要翻译：一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件，其中半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多个第一行中的对应的第一行和存储单元的第二端连接到多条第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

6. 发明授权

US07668007B2 Memory system including a resistance variable memory device 有权
标题翻译：存储器系统包括电阻变量存储器件
公开(公告)号：US07668007B2
公开(公告)日：2010-02-23
申请号：US12124523
申请日：2008-05-21
申请人： Byung-Gil Choi , Woo-Yeong Cho , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
发明人： Byung-Gil Choi , Woo-Yeong Cho , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/72
摘要： A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.
摘要翻译：存储器系统包括电阻可变存储器件和用于控制电阻变化存储器件的存储器控制器。电阻可变存储器件包括连接到位线的存储单元，适于从外部提供的电源电压产生高电压的高压电路，其中高电压高于电源电压，预充电电路适于充电位线到电源电压并进一步将位线充电到高电压，偏置电路适于使用高电压向位线提供读取电流;以及读出放大器，其适于使用来检测位线的电压电平高电压。

7. 发明申请

US20080232161A1 RESISTANCE VARIABLE MEMORY DEVICE AND READ METHOD THEREOF 有权
标题翻译：电阻可变存储器件及其读取方法
公开(公告)号：US20080232161A1
公开(公告)日：2008-09-25
申请号：US12124523
申请日：2008-05-21
申请人： Byung-Gil Choi , Woo-Yeong Cho , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
发明人： Byung-Gil Choi , Woo-Yeong Cho , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/72
摘要： A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.
摘要翻译：存储器系统包括电阻可变存储器件和用于控制电阻变化存储器件的存储器控制器。电阻可变存储器件包括连接到位线的存储单元，适于从外部提供的电源电压产生高电压的高压电路，其中高电压高于电源电压，预充电电路适于充电位线到电源电压并进一步将位线充电到高电压，偏置电路适于使用高电压向位线提供读取电流;以及读出放大器，其适于使用来检测位线的电压电平高电压。

8. 发明授权

US07061795B2 Magnetic random access memory device 失效
标题翻译：磁性随机存取存储器件
公开(公告)号：US07061795B2
公开(公告)日：2006-06-13
申请号：US10828894
申请日：2004-04-20
申请人： Hyung-Rok Oh , Woo-Yeong Cho , Su-Yeon Kim
发明人： Hyung-Rok Oh , Woo-Yeong Cho , Su-Yeon Kim
IPC分类号： G11C11/00 , G11C11/14
CPC分类号： G11C11/15
摘要： A magnetic random access memory device includes a digit line, a bit line, and a magnetic memory cell disposed in an intersection between the digit line and the bit line. The digit line is extended in a first direction on a substrate. The bit line is extended in a second direction on the substrate. The magnetic memory cell includes a rectangular free magnetic layer magnetized in a direction according to an externally applied magnetic field. A major axis of the rectangular free magnetic layer is substantially parallel to the first direction, and a minor axis of the rectangular free magnetic layer is substantially parallel to the second direction. Thus, multiple input/output program (write) operations and multiple input/output repair operations may be effectively performed.
摘要翻译：磁性随机存取存储器件包括设置在数字线和位线之间的交叉点中的数字线，位线和磁存储单元。数字线在衬底上沿第一方向延伸。位线在衬底上沿第二方向延伸。磁存储单元包括沿着外部施加的磁场的方向磁化的矩形自由磁性层。矩形自由磁性层的长轴基本上平行于第一方向，矩形自由磁性层的短轴基本上平行于第二方向。因此，可以有效地执行多个输入/输出程序（写入）操作和多个输入/输出修复操作。

9. 发明授权

US06982913B2 Data read circuit for use in a semiconductor memory and a memory thereof 有权
标题翻译：用于半导体存储器的数据读取电路及其存储器
公开(公告)号：US06982913B2
公开(公告)日：2006-01-03
申请号：US10943300
申请日：2004-09-17
申请人： Hyung-Rok Oh , Woo-Yeong Cho , Choong-Keun Kwak
发明人： Hyung-Rok Oh , Woo-Yeong Cho , Choong-Keun Kwak
IPC分类号： G11C7/00
CPC分类号： G11C13/004 , G11C7/06 , G11C7/12 , G11C13/0004 , G11C13/0026 , G11C2013/0054 , G11C2207/005
摘要： A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying a clamp voltage having a level for a read operation to a bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging a sensing node to a voltage having a power source level in response to a control signal of a first state in a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line in response to a control signal of a second state in a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level, and for sensing data stored in the selected unit cell.
摘要翻译：提供了一种用于具有存储单元阵列的半导体存储器件中的数据读取电路和方法。该电路包括：选择器，用于响应于地址信号选择存储单元阵列内的单位单元; 夹紧单元，用于响应于钳位控制信号，将具有用于读取操作的电平的钳位电压提供给所选择的单位单元的位线; 预充电单元，用于响应于在预充电模式中的第一状态的控制信号而将感测节点预充电到具有电源电平的电压，并且响应于位线在位线处减小的电流量补偿在数据感测模式中的第二状态的控制信号; 以及感测放大器单元，用于将感测节点的电平与参考电平进行比较，并且用于感测存储在所选择的单位单元中的数据。

10. 发明授权

US06943395B2 Phase random access memory with high density 有权
公开(公告)号：US06943395B2
公开(公告)日：2005-09-13
申请号：US10805696
申请日：2004-03-22
申请人： Hyung-Rok Oh , Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
发明人： Hyung-Rok Oh , Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G11C13/00 , G11B7/24 , G11C11/56 , G11C16/02 , H01L27/10 , H01L27/105 , H01L27/24 , H01L29/76 , H01L45/00 , H01L47/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/122 , H01L45/144
摘要： A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式