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1. 发明授权

US08219938B2 Semiconductor inter-field dose correction 有权
标题翻译：半导体场间剂量校正
公开(公告)号：US08219938B2
公开(公告)日：2012-07-10
申请号：US12580347
申请日：2009-10-16
申请人： Hyung-Rae Lee , Dong hee Yu , Len Y. Tsou , Haoren Zhuang
发明人： Hyung-Rae Lee , Dong hee Yu , Len Y. Tsou , Haoren Zhuang
IPC分类号： G06F17/50
CPC分类号： G03F1/00 , G03F7/70558
摘要： A method and apparatus are provided for adapting a semiconductor inter-field dose correction map from a first photolithography mask to a second photolithography mask using the same manufacturing stack and reactive ion etching processes, the method including: obtaining a first dose correction map for the first photolithography mask as a function of first chip or die identities; determining a first transformation matrix from the first chip or die identities of the first photolithography mask into an orthogonal coordinate system; determining a second transformation matrix from second chip or die identities of the second photolithography mask into the orthogonal coordinate system; and transforming the first dose correction map for the first photolithography mask into a second dose correction map for the second photolithography mask in correspondence with each of the first and second transformation matrices.
摘要翻译：提供了一种方法和装置，用于使用相同的制造堆叠和反应离子蚀刻工艺，将半导体场间剂量校正图从第一光刻掩模适配到第二光刻掩模，该方法包括：获得第一光刻掩模的第一剂量校正图光刻掩模作为第一芯片或芯片标识的函数; 将第一光刻掩模的第一芯片或裸片标识的第一变换矩阵确定为正交坐标系; 确定从所述第二光刻掩模的第二芯片或裸片标识到所述正交坐标系的第二变换矩阵; 以及将第一光刻掩模的第一剂量校正图转换成与第一和第二变换矩阵中的每一个对应的第二光刻掩模的第二剂量校正图。

2. 发明申请

US20110093823A1 SEMICONDUCTOR INTER-FIELD DOSE CORRECTION 有权
标题翻译：半导体场效应校正
公开(公告)号：US20110093823A1
公开(公告)日：2011-04-21
申请号：US12580347
申请日：2009-10-16
申请人： Hyung-Rae Lee , Dong Hee Yu , Len Y. Tsou , Haoren Zhuang
发明人： Hyung-Rae Lee , Dong Hee Yu , Len Y. Tsou , Haoren Zhuang
IPC分类号： G06F17/50
CPC分类号： G03F1/00 , G03F7/70558
摘要： A method and apparatus are provided for adapting a semiconductor inter-field dose correction map from a first photolithography mask to a second photolithography mask using the same manufacturing stack and reactive ion etching processes, the method including: obtaining a first dose correction map for the first photolithography mask as a function of first chip or die identities; determining a first transformation matrix from the first chip or die identities of the first photolithography mask into an orthogonal coordinate system; determining a second transformation matrix from second chip or die identities of the second photolithography mask into the orthogonal coordinate system; and transforming the first dose correction map for the first photolithography mask into a second dose correction map for the second photolithography mask in correspondence with each of the first and second transformation matrices.
摘要翻译：提供了一种方法和装置，用于使用相同的制造堆叠和反应离子蚀刻工艺，将半导体场间剂量校正图从第一光刻掩模适配到第二光刻掩模，该方法包括：获得第一光刻掩模的第一剂量校正图光刻掩模作为第一芯片或芯片标识的函数; 将第一光刻掩模的第一芯片或裸片标识的第一变换矩阵确定为正交坐标系; 确定从所述第二光刻掩模的第二芯片或裸片标识到所述正交坐标系的第二变换矩阵; 以及将第一光刻掩模的第一剂量校正图转换成与第一和第二变换矩阵中的每一个对应的第二光刻掩模的第二剂量校正图。

3. 发明授权

US06960510B2 Method of making sub-lithographic features 失效
标题翻译：制作亚光刻特征的方法
公开(公告)号：US06960510B2
公开(公告)日：2005-11-01
申请号：US10187579
申请日：2002-07-01
申请人： Sadanand V. Deshpande , Toshiharu Furukawa , David V. Horak , Wesley C. Natzle , Akihisa Sekiguchi , Len Y. Tsou , Qingyun Yang
发明人： Sadanand V. Deshpande , Toshiharu Furukawa , David V. Horak , Wesley C. Natzle , Akihisa Sekiguchi , Len Y. Tsou , Qingyun Yang
IPC分类号： H01L21/033 , H01L21/265 , H01L21/28 , H01L21/308 , H01L21/311 , H01L21/8238 , H01L21/336 , H01L21/8234 , H01L21/8236
CPC分类号： H01L21/26586 , H01L21/0337 , H01L21/0338 , H01L21/2815 , H01L21/3086 , H01L21/3088 , H01L21/31144
摘要： A method of forming a structure having sub-lithographic dimensions is provided. The method includes: forming a chamfered mandrel on a substrate, the mandrel having an angled surface; and performing an angled ion implantation to obtain an implanted shadow region in the substrate, the implanted shadow mask having at least one sub-lithographic dimension.
摘要翻译：提供了形成具有亚光刻尺寸的结构的方法。该方法包括：在基底上形成倒角心轴，心轴具有成角度的表面; 以及执行成角度的离子注入以在所述衬底中获得注入的阴影区域，所述植入的荫罩具有至少一个亚光刻尺寸。

4. 发明授权

US06864041B2 Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching 失效
标题翻译：使用等离子体蚀刻的100nm以下器件的栅极线宽定制和临界尺寸控制
公开(公告)号：US06864041B2
公开(公告)日：2005-03-08
申请号：US09847479
申请日：2001-05-02
申请人： Jeffrey J. Brown , Sadanand Vinayak Deshpande , David V. Horak , Maheswaran Surendra , Len Y. Tsou , Qingyun Yang , Chienfan Yu , Ying Zhang
发明人： Jeffrey J. Brown , Sadanand Vinayak Deshpande , David V. Horak , Maheswaran Surendra , Len Y. Tsou , Qingyun Yang , Chienfan Yu , Ying Zhang
IPC分类号： G03F7/40 , G03F7/42 , H01L21/033 , G03F7/36 , H01L21/461
CPC分类号： G03F7/40 , G03F7/427 , H01L21/0337 , H01L21/0338
摘要： A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.
摘要翻译：一种在晶片上制造电子芯片的方法，其中在晶片上形成以预定的较低分辨率的第一掩模，然后在第一组条件下在预定时间段内蚀刻以实现低于电流分辨率极限的掩模平版印刷然后将蚀刻的掩模用作用于在下层上蚀刻材料的硬掩模。

5. 发明授权

US5286337A Reactive ion etching or indium tin oxide 失效
标题翻译：反应离子蚀刻或氧化铟锡
公开(公告)号：US5286337A
公开(公告)日：1994-02-15
申请号：US8116
申请日：1993-01-25
申请人： Len Y. Tsou
发明人： Len Y. Tsou
IPC分类号： C01G19/00 , C04B41/53 , C04B41/91 , C23F4/00 , G02F1/1343 , H01L21/302 , H01L21/3065 , H01L31/18 , B01J15/00
CPC分类号： C04B41/009 , C04B41/5346 , C04B41/91 , H01L31/1884 , C04B2111/00844 , Y02E10/50
摘要： Indium tin oxide films deposited on substrates are subjected to reactive ion etching in a plasma containing dissociated hydrogen bromide or a mixture of dissociated hydrogen bromide and dissociated boron tinchloride.
摘要翻译：沉积在基板上的氧化铟锡膜在包含解离的溴化氢或解离的溴化氢和离解的氯化锡的混合物的等离子体中进行反应离子蚀刻。

6. 发明授权

US06884734B2 Vapor phase etch trim structure with top etch blocking layer 失效
标题翻译：具有顶部蚀刻阻挡层的气相蚀刻修整结构
公开(公告)号：US06884734B2
公开(公告)日：2005-04-26
申请号：US09989822
申请日：2001-11-20
申请人： Frederick W. Buehrer , Derek Chen , William Chu , Scott Crowder , Sadanand V. Deshpande , David V. Horak , Wesley C. Natzle , Hung Y. Ng , Len Y. Tsou , Chienfan Yu
发明人： Frederick W. Buehrer , Derek Chen , William Chu , Scott Crowder , Sadanand V. Deshpande , David V. Horak , Wesley C. Natzle , Hung Y. Ng , Len Y. Tsou , Chienfan Yu
IPC分类号： H01L21/033 , H01L21/28 , H01L21/302 , H01L21/3205 , H01L21/3213 , H01L21/461 , H01L21/8234
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/28123
摘要： A blocking layer is formed on a hard mask having an initial thickness. Lines are fabricated by patterning the blocking layer and the hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segment to form a layer of a reaction product on a remaining portion of the line segment; and removing the reaction product without attacking the remaining portion of the line segment and without attacking the blocking layer and the substrate to form the line segment with a second dimension across the line segment that is smaller than the first dimension. The blocking layer prevents the formation of reaction product on the hard mask so that the initial thickness of the hard mask is maintained. The blocking layer can also serve as an ARC layer for photoresist patterning so that the use of an additional film layer is not required.
摘要翻译：在具有初始厚度的硬掩模上形成阻挡层。线通过图案化阻挡层和硬掩模来制造以提供线段，线段具有跨越线段测量的第一尺寸; 使所述线段的表面层反应以在所述线段的剩余部分上形成反应产物层; 并且除去反应产物而不攻击线段的剩余部分，而不攻击阻挡层和基底，以形成跨越比第一尺寸小的线段的具有第二尺寸的线段。阻挡层防止在硬掩模上形成反应产物，从而保持硬掩模的初始厚度。阻挡层也可以用作光致抗蚀剂图案化的ARC层，从而不需要使用附加的膜层。

7. 发明授权

US06509219B2 Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch 失效
公开(公告)号：US06509219B2
公开(公告)日：2003-01-21
申请号：US09928212
申请日：2001-08-10
申请人： Len Y. Tsou , Hongwen Yan , Qingyun Yang , Chienfan Yu
发明人： Len Y. Tsou , Hongwen Yan , Qingyun Yang , Chienfan Yu
IPC分类号： H01L21336
CPC分类号： H01L21/28114 , H01L29/42376
摘要： A method of forming a notched gate structure having substantially vertical sidewalls and a sub-0.05 &mgr;m electrical critical dimension is provided. The method includes forming a conductive layer on an insulating layer; forming a mask on the conductive layer so as to at least protect a portion of the conductive layer; anisotropically etching the conductive layer not protected by the mask so as to thin the conductive layer to a predetermined thickness and to form a conductive feature underlying the mask, the conductive feature having substantially vertical sidewalls; forming a passivating layer at least on the substantially vertical sidewalls; and isotropically etching remaining conductive layer not protected by the mask to remove the predetermined thickness thereby exposing a lower portion of said conductive feature not containing the passivating layer, while simultaneously removing notched regions in the lower portion of the conductive feature.

8. 发明授权

US06828187B1 Method for uniform reactive ion etching of dual pre-doped polysilicon regions 失效
标题翻译：双预掺杂多晶硅区域的均匀反应离子蚀刻方法
公开(公告)号：US06828187B1
公开(公告)日：2004-12-07
申请号：US10707709
申请日：2004-01-06
申请人： Joyce C. Liu , Len Y. Tsou , Qingyun Yang
发明人： Joyce C. Liu , Len Y. Tsou , Qingyun Yang
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , H01L21/28035 , H01L21/32137
摘要： A method for forming a semiconductor device, includes forming a first locally doped semiconductor region of a first conductivity type and a second locally doped semiconductor region of a second conductivity type over an undoped, lower semiconductor region. A first etch is implemented to simultaneously create a desired pattern in the first and second locally doped semiconductor regions in a manner that also provides a first passivation of exposed sidewalls thereof, wherein the first etch removes material from the first and second locally doped regions at a substantially constant rate with respect to one another, and in a substantially anisotropic manner. A second etch is implemented to complete the desired pattern in the undoped, lower semiconductor region in a manner that protects the first and second locally doped regions from additional material removal therefrom.
摘要翻译：一种用于形成半导体器件的方法，包括在未掺杂的下半导体区域上形成第一导电类型的第一局部掺杂半导体区域和第二导电类型的第二局部掺杂半导体区域。实施第一蚀刻以在第一和第二局部掺杂的半导体区域中以提供其暴露的侧壁的第一钝化的方式同时产生期望的图案，其中第一蚀刻从第一和第二局部掺杂区域中去除材料相对于基本上恒定的速率，并且以基本上各向异性的方式。实现第二蚀刻以在未掺杂的较低半导体区域中以保护第一和第二局部掺杂区域免除额外材料的方式完成所需图案。

9. 发明授权

US06703269B2 Method to form gate conductor structures of dual doped polysilicon 有权
标题翻译：形成双掺杂多晶硅栅极导体结构的方法
公开(公告)号：US06703269B2
公开(公告)日：2004-03-09
申请号：US10114829
申请日：2002-04-02
申请人： Jeffrey J. Brown , Len Y. Tsou , Qingyun Yang
发明人： Jeffrey J. Brown , Len Y. Tsou , Qingyun Yang
IPC分类号： H01L218238
CPC分类号： H01L21/823842
摘要： A method for manufacturing a semiconductor chip which has transistors is disclosed. The transistors include first type transistors which have a first type of doping and second type transistors which have a second type of doping different than the first type of doping. The method includes forming a conductive layer on a substrate. The conductive layer includes first regions that have the first type of doping and second regions have the second type of doping. The invention patterns a mask over the conductive layer, and the mask protects portions of the conductive layer where gate conductors will be located. Next, the invention partially etches unprotected portions of the conductive layer. The partially etching process allows a layer of the unprotected portions to remain, such that the substrate is not exposed by the partially etching process. The invention forms a passivating layer on exposed vertical surfaces of the conductive layer and completely etches unprotected portions of the conductive layer to expose the substrate. The invention then dopes exposed portions of the substrate to form source/drain regions.
摘要翻译：公开了一种制造具有晶体管的半导体芯片的方法。晶体管包括具有第一类型掺杂的第一类型晶体管和具有不同于第一类型掺杂的第二类型掺杂的第二类型晶体管。该方法包括在衬底上形成导电层。导电层包括具有第一类型的掺杂的第一区域和第二区域具有第二类型的掺杂。本发明在导电层上形成掩模，并且掩模保护导电层在栅极导体将被定位的部分。接下来，本发明部分地蚀刻导电层的未受保护的部分。部分蚀刻工艺允许保留未保护部分的层，使得基板不被部分蚀刻工艺暴露。本发明在导电层的暴露的垂直表面上形成钝化层，并且完全蚀刻导电层的未受保护的部分以暴露衬底。然后，本发明掺杂衬底的暴露部分以形成源极/漏极区域。

10. 发明授权

US4491499A Optical emission end point detector 失效
标题翻译：光发射终点探测器
公开(公告)号：US4491499A
公开(公告)日：1985-01-01
申请号：US594629
申请日：1984-03-29
申请人： Leslie G. Jerde , Earl R. Lory , Kevin A. Muething , Len Y. Tsou
发明人： Leslie G. Jerde , Earl R. Lory , Kevin A. Muething , Len Y. Tsou
IPC分类号： C23F4/00 , G01N21/62 , H01J37/32 , C23F1/00 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01J37/32935 , C23F4/00 , G01N21/62
摘要： A method for determining the optimum time at which a plasma etching operation should be terminated. The optical emission intensity (S.sub.1) of the plasma in a narrow band centered about a predetermined spectral line, indicative of the gas phase concentration of a plasma etch product or reactant species. The optical emission intensity (S.sub.2) of the plasma in a wide band centered about the predetermined spectral line, indicative of a background emission signal is also monitored. The intensity (S.sub.1L) of the spectral line is then determined in accordance with the equation S.sub.1L =S.sub.1 -k (.alpha.S.sub.2 -S.sub.1). The etching process is terminated when the monitored signal intensity (S.sub.1L) or its time derivative reaches a predetermined value.
摘要翻译：一种用于确定终止等离子体蚀刻操作的最佳时间的方法。以围绕预定光谱线为中心的窄带中的等离子体的光发射强度（S1），其指示等离子体蚀刻产物或反应物物质的气相浓度。也监视指示背景发射信号的预定光谱线中心的宽带中的等离子体的光发射强度（S2）。然后根据等式S1L = S1-k（α2S-S1）确定谱线的强度（S1L）。当监视信号强度（S1L）或其时间导数达到预定值时，蚀刻过程终止。

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