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    • 2. 发明授权
    • SOI device with double gate and method for fabricating the same
    • 具有双栅极的SOI器件及其制造方法
    • US06352872B1
    • 2002-03-05
    • US09712705
    • 2000-11-14
    • Hyung Ki KimJong Wook Lee
    • Hyung Ki KimJong Wook Lee
    • H01L21338
    • H01L29/66772H01L29/42384H01L29/4908H01L29/78648
    • A silicon-on-insulator (SOI) device having a double gate, comprising: a supporting substrate; a first insulating layer formed over the supporting substrate; a first silicon layer formed over the first insulating layer, the first silicon layer including a first impurity region of a first conductivity disposed in a central portion thereof and intrinsic regions disposed at the both sides of the first impurity region; a second insulating layer formed over the first silicon layer; a second silicon layer formed over the second insulating layer, the second silicon layer including a second impurity region of a second conductivity disposed in a central portion thereof and third impurity regions of first conductivities disposed at the both sides of the second impurity region; a third insulating layer formed over the second impurity region; and a polysilicon layer doped with impurity ions of first conductivities, formed over the third insulating layer.
    • 一种具有双栅极的绝缘体上硅(SOI)器件,包括:支撑衬底; 形成在所述支撑基板上的第一绝缘层; 形成在所述第一绝缘层上的第一硅层,所述第一硅层包括设置在所述第一绝缘层的中心部分的第一导电性的第一杂质区和设置在所述第一杂质区两侧的本征区; 形成在所述第一硅层上的第二绝缘层; 形成在所述第二绝缘层上的第二硅层,所述第二硅层包括布置在其中心部分的具有第二导电性的第二杂质区和设置在所述第二杂质区两侧的第一导电性的第三杂质区; 形成在第二杂质区上的第三绝缘层; 以及在第三绝缘层上形成掺杂有第一导电性的杂质离子的多晶硅层。
    • 3. 发明授权
    • Method for fabricating semiconductor device
    • 制造半导体器件的方法
    • US06168979A
    • 2001-01-02
    • US09348572
    • 1999-07-07
    • Hyung Ki KimJong Wook Lee
    • Hyung Ki KimJong Wook Lee
    • H01L2972
    • H01L27/1203H01L21/84
    • Disclosed is a semiconductor device having low voltage characteristic and advantageous integrity simultaneously. The semiconductor device comprises a silicon-on-insulator (SOI) substrate of a stack structure comprising a base layer as a means for supporting, a buried oxide layer, and a semiconductor layer providing an active region; and a first transistor and a second transistor formed on the active region of the SOI substrate, wherein the first and second transistors are formed as a stack structure on one active region and they share one gate electrode, a drain region of the second transistor is electrically connected to the gate electrode and a source region of the second transistor is electrically connected to the active region.
    • 公开了具有低电压特性和有利完整性的半导体器件。 半导体器件包括堆叠结构的绝缘体上硅(SOI)衬底,其包括作为支撑的器件的基底层,掩埋氧化物层和提供有源区的半导体层; 以及形成在所述SOI衬底的有源区上的第一晶体管和第二晶体管,其中所述第一和第二晶体管形成为在一个有源区上的堆叠结构,并且它们共享一个栅电极,所述第二晶体管的漏区电 连接到栅电极,并且第二晶体管的源极区域电连接到有源区。
    • 6. 发明申请
    • Hydrogen supply system for fuel cell
    • 燃料电池用氢系统
    • US20100167155A1
    • 2010-07-01
    • US11999370
    • 2007-12-04
    • Sang Hyun KimHoon Hee LeeHyung Ki Kim
    • Sang Hyun KimHoon Hee LeeHyung Ki Kim
    • H01M8/24
    • H01M8/04201F17C5/06F17C11/005F17C2221/012H01M8/04089H01M8/04216Y02E60/321Y10T137/4673Y10T137/469
    • The present invention provides a hydrogen supply system for a fuel cell which can compensate for a change in temperature, caused by heat generated when a high pressure tank is charged and discharged with hydrogen, using a metal hydride (MH) tank providing high hydrogen storage density, mounted in the high pressure tank such that hydrogen is to be discharged from the MH tank when hydrogen is charged to the high pressure tank, and hydrogen is to be charged to the MH tank when hydrogen is discharged from the high pressure tank.For this, the present invention provides a hydrogen supply system for a fuel cell, including: a high pressure tank which is capable of storing hydrogen received from a hydrogen refueling station and includes a metal hydride (MH) tank capable of storing hydrogen, mounted therein; first and second solenoid valves provided at both ends of the high pressure tank; a buffer tank connected in parallel to the high pressure tank; and a fuel cell stack connected to the buffer tank so that hydrogen from the high pressure tank or the MH tank is supplied to the stack through the buffer tank, wherein the hydrogen is charged from the hydrogen refueling station to the high pressure tank and discharged from the high pressure tank through the first solenoid valve, the hydrogen is charged and discharged to and from the MH tank through the second solenoid valve, the hydrogen is discharged from the MH tank as the first and second solenoid valves are simultaneously opened when the hydrogen is charged to the high pressure tank, and the hydrogen discharged from the MH tank is stored in the buffer tank and then supplied to the fuel cell stack.
    • 本发明提供了一种用于燃料电池的氢气供应系统,其能够补偿当高压罐用氢气充放电时产生的热引起的温度变化,使用提供高储氢密度的金属氢化物(MH) 安装在高压罐中,以便当氢气被充入高压罐时氢从MH储存器中排出,当氢气从高压罐排出时,氢气将被充入MH储罐。 为此,本发明提供了一种用于燃料电池的氢气供应系统,包括:高压罐,其能够储存从加氢站接收的氢气,并且包括能够储存氢的金属氢化物(MH)罐,安装在其中 ; 设置在高压罐两端的第一和第二电磁阀; 与高压罐并联连接的缓冲罐; 以及连接到缓冲罐的燃料电池堆,使得来自高压罐或MH箱的氢气通过缓冲罐被供应到堆叠,其中氢气从加氢站被加载到高压罐并从 高压罐通过第一电磁阀,氢气通过第二电磁阀向MH箱充放电,当氢气为氢时,第一和第二电磁阀同时打开时氢从MH箱排出 充入高压罐,从MH箱排出的氢气储存在缓冲罐中,然后供给到燃料电池堆。
    • 7. 发明授权
    • Method for forming bit-line of semiconductor device
    • 形成半导体器件位线的方法
    • US07101783B2
    • 2006-09-05
    • US10879299
    • 2004-06-30
    • Hyung Ki Kim
    • Hyung Ki Kim
    • H01L21/4763
    • H01L21/32051H01L27/10888H01L27/10894
    • Disclosed is a method for forming a bit-line of a semiconductor device. In a line patterning process for forming a bit-line in a DRAM (Dynamic Random Access Memory) of a semiconductor device, a barrier metal layer and a tungsten layer are sequentially formed on an interlayer insulating film comprising a contact hole to fill the contact hole by a CVD (Chemical Vapor Deposition) method. Then, the barrier metal layer and the tungsten layer are removed until the interlayer insulating film is exposed, and a tungsten layer having small thickness is re-formed on the exposed interlayer insulating film by a PVD (physical Vapor Deposition) method. As a result, the bit-line area is reduced as much as the barrier metal layer removed from the upper portion of interlayer insulating film, thereby having low bit-line capacitance.
    • 公开了一种形成半导体器件的位线的方法。 在用于在半导体器件的DRAM(动态随机存取存储器)中形成位线的线图案化工艺中,阻挡金属层和钨层依次形成在包括接触孔的层间绝缘膜上以填充接触孔 通过CVD(化学气相沉积)法。 然后,去除阻挡金属层和钨层,直到层间绝缘膜露出,并且通过PVD(物理气相沉积)方法在暴露的层间绝缘膜上重新形成厚度小的钨层。 结果,位线区域与从层间绝缘膜的上部去除的阻挡金属层一样减少,从而具有低的位线电容。