专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09384837B2 Method of erasing memory cells when changing their mode of operation within a nonvolatile memory device 有权
标题翻译：在非易失性存储器件中改变其操作模式时擦除存储器单元的方法
公开(公告)号：US09384837B2
公开(公告)日：2016-07-05
申请号：US14467920
申请日：2014-08-25
申请人： Hyun-Wook Park , Kitae Park , Jaeyong Jeong
发明人： Hyun-Wook Park , Kitae Park , Jaeyong Jeong
IPC分类号： G11C16/04 , G11C16/14 , G11C16/34
CPC分类号： G11C16/14 , G11C11/56 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3418 , G11C16/3445
摘要： An method of operating a memory system including a plurality of memory cells includes changing an operation mode at least some of the memory cells which operate based on a first operation mode to operate based on a second operation mode; and performing a change erase operation on the memory cells for which an operation mode is changed on the basis of a change erase condition when the operation mode is changed. When memory cells operate in the first operation mode, a normal erase operation is performed based on a first erase condition, and when memory cells operate in the second operation mode, a normal erase operation is performed based on a second erase condition. The change erase condition is different from at least one of the first and second erase conditions.
摘要翻译：一种操作包括多个存储器单元的存储器系统的方法包括：根据第二操作模式，改变基于第一操作模式操作的至少一些存储器单元的操作模式; 并且当操作模式改变时，基于改变擦除条件，对在其中改变操作模式的存储单元执行改变擦除操作。当存储单元在第一操作模式下工作时，基于第一擦除条件执行正常擦除操作，并且当存储器单元在第二操作模式下操作时，基于第二擦除条件执行正常擦除操作。改变擦除条件不同于第一和第二擦除条件中的至少一个。

2. 发明授权

US09021338B2 Memory system and data storage method 有权
标题翻译：内存系统和数据存储方式
公开(公告)号：US09021338B2
公开(公告)日：2015-04-28
申请号：US13604772
申请日：2012-09-06
申请人： Sang-Hyun Joo , Kitae Park , Sangyong Yoon , Jaeyong Jeong
发明人： Sang-Hyun Joo , Kitae Park , Sangyong Yoon , Jaeyong Jeong
IPC分类号： G06F11/10 , G11C29/42 , G06F3/06 , H03M13/05 , H03M13/37 , G06F12/02 , G06F11/14
CPC分类号： G06F11/1048 , G06F3/0649 , G06F11/1068 , G06F11/14 , G06F11/1402 , G06F12/0246 , G06F2212/72 , G06F2212/7205 , G11C29/42 , G11C2211/5641 , H03M13/05 , H03M13/3715
摘要： A memory system comprises a nonvolatile memory device comprising a memory cell array comprising first and second memory blocks, and a memory controller configured to control the nonvolatile memory device to read data from the first memory block, selectively determine an error correction operation to be performed on the data after it is read from the first memory block based on a state of at least one of the first and second memory blocks, and then store the data in the second memory block.
摘要翻译：存储器系统包括非易失性存储器件，其包括包括第一和第二存储器块的存储器单元阵列，以及存储器控制器，其被配置为控制非易失性存储器件从第一存储器块读取数据，选择性地确定要执行的纠错操作基于第一和第二存储器块中的至少一个的状态从第一存储器块读取之后的数据，然后将数据存储在第二存储器块中。

3. 发明授权

US08861276B2 Nonvolatile memory device, memory system comprising same, and method of operating same 有权
标题翻译：非易失性存储器件，包括其的存储器系统及其操作方法
公开(公告)号：US08861276B2
公开(公告)日：2014-10-14
申请号：US13527641
申请日：2012-06-20
申请人： Dongkyo Shim , Jaeyong Jeong , Ju Seok Lee , Ohsuk Kwon , Kitae Park , Hyunjun Yoon
发明人： Dongkyo Shim , Jaeyong Jeong , Ju Seok Lee , Ohsuk Kwon , Kitae Park , Hyunjun Yoon
IPC分类号： G11C16/26 , G11C16/04 , G11C11/56
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483
摘要： A method of operating a nonvolatile memory device comprises receiving a read command from a memory controller, determining a read mode of the nonvolatile memory device, selecting a read voltage based on the read mode, and performing a read operation on memory cells of a selected page of the nonvolatile memory device using the selected read voltage.
摘要翻译：一种操作非易失性存储器件的方法包括从存储器控制器接收读取命令，确定非易失性存储器件的读取模式，基于读取模式选择读取电压，以及对所选择的页面的存储器单元执行读取操作使用所选择的读取电压的非易失性存储器件。

4. 发明授权

US09733864B2 Memory system including nonvolatile memory device and erase method thereof 有权
公开(公告)号：US09733864B2
公开(公告)日：2017-08-15
申请号：US14527092
申请日：2014-10-29
申请人： Sangkwon Moon , Jihong Kim , Jaeyong Jeong , Kyung Ho Kim
发明人： Sangkwon Moon , Jihong Kim , Jaeyong Jeong , Kyung Ho Kim
IPC分类号： G06F3/06 , G06F12/02
CPC分类号： G06F3/0652 , G06F3/0616 , G06F3/0679 , G06F12/0246 , G06F2212/72
摘要： An erase method of a nonvolatile memory device is provided which includes receiving an erase request; selecting an erase mode of a memory block corresponding to the erase request, based on an access condition of the nonvolatile memory device managed by a memory controller; and controlling the nonvolatile memory device to erase the memory block according to the selected erase mode. The erase mode includes a fast erase mode of which an erase time for the memory block is shorter than a reference time and a slow erase mode of which an erase time for the memory block is longer than the reference time.

5. 发明申请

US20110145485A1 METHOD FOR MANAGING ADDRESS MAPPING TABLE AND A MEMORY DEVICE USING THE METHOD 审中-公开
标题翻译：用于管理地址映射表的方法和使用该方法的存储器件
公开(公告)号：US20110145485A1
公开(公告)日：2011-06-16
申请号：US12946893
申请日：2010-11-16
申请人： Jin-Young Chun , Jaeyong Jeong
发明人： Jin-Young Chun , Jaeyong Jeong
IPC分类号： G06F12/10 , G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： An address mapping table includes arrays each being allocated to a logical address and in which a physical address mapping the logical address is stored. In the case where the physical address mapped to the logical address is changed, a value of a difference between a pre-changed physical address and a physical address to be changed is stored in the address mapping table. When the logical address is mapped to the physical address, the mapped physical address is calculated by adding up the logical address and values stored in the arrays allocated to the logical address. The address mapping table is managed to decrease the number of erase counts of a memory device in which the address mapping table is stored.
摘要翻译：地址映射表包括分配给逻辑地址的阵列，并且存储映射逻辑地址的物理地址。在映射到逻辑地址的物理地址被改变的情况下，预先改变的物理地址和要改变的物理地址之间的差值被存储在地址映射表中。当逻辑地址映射到物理地址时，通过将逻辑地址和存储在分配给逻辑地址的阵列中的值相加来计算映射的物理地址。管理地址映射表以减少存储地址映射表的存储器件的擦除次数。

6. 发明授权

US09646705B2 Memory systems including nonvolatile memory devices and dynamic access methods thereof 有权
公开(公告)号：US09646705B2
公开(公告)日：2017-05-09
申请号：US14287580
申请日：2014-05-27
申请人： Sangkwon Moon , Kyung Ho Kim , Jihong Kim , Jaeyong Jeong
发明人： Sangkwon Moon , Kyung Ho Kim , Jihong Kim , Jaeyong Jeong
IPC分类号： G11C16/16 , G11C16/26 , G11C11/56 , G11C16/34
CPC分类号： G11C16/16 , G11C11/5635 , G11C16/26 , G11C16/349
摘要： A method of operating a memory device includes: determining an erase mode based on a number of erase cycles performed on a memory block and an erase voltage utilized to perform each erase cycle; and setting an erase voltage level for executing an erase operation on the memory block based on the determined erase mode.

7. 发明授权

US08976595B2 Non-volatile memory device and related method of operation 有权
标题翻译：非易失性存储器件及相关操作方法
公开(公告)号：US08976595B2
公开(公告)日：2015-03-10
申请号：US13526794
申请日：2012-06-19
申请人： Jaeyong Jeong , Ju Seok Lee
发明人： Jaeyong Jeong , Ju Seok Lee
IPC分类号： G11C16/00 , G11C11/56 , G11C16/26 , G11C16/34
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/24 , G11C16/3454
摘要： A nonvolatile memory device comprises a cell array connected to a plurality of bit lines in an all bit line structure, a page buffer circuit connected to the plurality of bit lines, and control logic configured to control the page buffer circuit. The control logic controls the page buffer circuit to sense memory cells corresponding to both even-numbered and odd-numbered columns of a selected page in a first read mode and to sense memory cells corresponding to one of the even-numbered and odd-numbered columns of the selected page in a second read mode. A sensing operation is performed at least twice in the first read mode and once in the second read mode.
摘要翻译：非易失性存储器件包括连接到全位线结构中的多个位线的单元阵列，连接到多个位线的寻址缓冲器电路以及被配置为控制页缓冲器电路的控制逻辑。控制逻辑控制页面缓冲电路以在第一读取模式中感测与选定页面的偶数和偶数列对应的存储器单元，并且读取对应于偶数和奇数列之一的存储器单元的第二读取模式。在第一读取模式下执行感测操作至少两次，并且在第二读取模式中执行一次感测操作。

8. 发明授权

US08705294B2 Nonvolatile memory and method of controlling thereof 有权
标题翻译：非易失性存储器及其控制方法
公开(公告)号：US08705294B2
公开(公告)日：2014-04-22
申请号：US13552668
申请日：2012-07-19
申请人： Jaeyong Jeong
发明人： Jaeyong Jeong
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C16/0483 , G11C16/20
摘要： A memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array storing setup data and reference data, and first and second latch units respectively configured to store the setup data and the reference data sensed from the memory cell array upon a power-up of the memory system. The controller is configured to control a sensing operation of the nonvolatile memory. An operating environment of the nonvolatile memory is determined by the setup data stored in the first latch unit, and the controller controls the nonvolatile memory to re-store the setup data of the memory cell array in the first latch unit when the reference data of the second latch unit is changed.
摘要翻译：存储器系统包括非易失性存储器和控制器。非易失性存储器包括存储设置数据和参考数据的存储单元阵列，以及第一和第二锁存单元，分别被配置为在存储器系统的加电时存储从存储单元阵列感测的建立数据和参考数据。控制器被配置为控制非易失性存储器的感测操作。非易失性存储器的操作环境由存储在第一锁存单元中的设置数据确定，并且当第一锁存单元的参考数据为“0”时，控制器控制该非易失性存储器以将存储单元阵列的建立数据重新存储在第一锁存单元中第二锁存单元被改变。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式