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1. 发明授权

US08314457B2 Non-volatile memory devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US08314457B2
公开(公告)日：2012-11-20
申请号：US13095408
申请日：2011-04-27
申请人： Hyun-Suk Kim , Sun-Il Shim , Chang-Seok Kang , Won-Cheol Jeong , Jung-Dal Choi , Jae-Kwan Park , Seung-Hyun Lim , Sun-Jung Kim
发明人： Hyun-Suk Kim , Sun-Il Shim , Chang-Seok Kang , Won-Cheol Jeong , Jung-Dal Choi , Jae-Kwan Park , Seung-Hyun Lim , Sun-Jung Kim
IPC分类号： H01L29/66
CPC分类号： H01L21/28282 , H01L29/42324 , H01L29/4234 , H01L29/7881 , H01L29/792
摘要： Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.
摘要翻译：提供了非易失性存储器件，其包括在衬底上的控制栅电极; 在控制栅电极和衬底之间的电荷存储绝缘层; 在电荷存储绝缘层和衬底之间的隧道绝缘层; 电荷存储绝缘层和控制栅电极之间的阻挡绝缘层; 以及隧道绝缘层和阻挡绝缘层之间的材料层，材料层具有构成势阱底部的能级。

2. 发明授权

US07973357B2 Non-volatile memory devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US07973357B2
公开(公告)日：2011-07-05
申请号：US12338308
申请日：2008-12-18
申请人： Hyun-Suk Kim , Sun-Il Shim , Chang-Seok Kang , Won-Cheol Jeong , Jung-Dal Choi , Jae-Kwan Park , Seung-Hyun Lim , Sun-Jung Kim
发明人： Hyun-Suk Kim , Sun-Il Shim , Chang-Seok Kang , Won-Cheol Jeong , Jung-Dal Choi , Jae-Kwan Park , Seung-Hyun Lim , Sun-Jung Kim
IPC分类号： H01L29/66
CPC分类号： H01L21/28282 , H01L29/42324 , H01L29/4234 , H01L29/7881 , H01L29/792
摘要： Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.
摘要翻译：提供了非易失性存储器件，其包括在衬底上的控制栅电极; 在控制栅电极和衬底之间的电荷存储绝缘层; 在电荷存储绝缘层和衬底之间的隧道绝缘层; 电荷存储绝缘层和控制栅电极之间的阻挡绝缘层; 以及隧道绝缘层和阻挡绝缘层之间的材料层，材料层具有构成势阱底部的能级。

3. 发明申请

US20110198685A1 Non-Volatile Memory Devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US20110198685A1
公开(公告)日：2011-08-18
申请号：US13095408
申请日：2011-04-27
申请人： Hyun-Suk Kim , Sun-II Shim , Chang-Seok Kang , Won-Cheol Jeong , Jung-Dal Choi , Jae-Kwan Park , Seung-Hyun Lim , Sun-Jung Kim
发明人： Hyun-Suk Kim , Sun-II Shim , Chang-Seok Kang , Won-Cheol Jeong , Jung-Dal Choi , Jae-Kwan Park , Seung-Hyun Lim , Sun-Jung Kim
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L29/42324 , H01L29/4234 , H01L29/7881 , H01L29/792
摘要： Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.
摘要翻译：提供了非易失性存储器件，其包括在衬底上的控制栅电极; 在控制栅电极和衬底之间的电荷存储绝缘层; 在电荷存储绝缘层和衬底之间的隧道绝缘层; 电荷存储绝缘层和控制栅电极之间的阻挡绝缘层; 以及隧道绝缘层和阻挡绝缘层之间的材料层，材料层具有构成势阱底部的能级。

4. 发明申请

US20090159962A1 Non-Volatile Memory Devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US20090159962A1
公开(公告)日：2009-06-25
申请号：US12338308
申请日：2008-12-18
申请人： Hyun Suk Kim , Sun-II Shim , Chang-Seok Kang , Won-Cheol Jeong , Jung-Dal Choi , Jae-Kwan Park , Seung-Hyun Lim , Sun-Jung Kim
发明人： Hyun Suk Kim , Sun-II Shim , Chang-Seok Kang , Won-Cheol Jeong , Jung-Dal Choi , Jae-Kwan Park , Seung-Hyun Lim , Sun-Jung Kim
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L29/42324 , H01L29/4234 , H01L29/7881 , H01L29/792
摘要： Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.
摘要翻译：提供了非易失性存储器件，其包括在衬底上的控制栅电极; 在控制栅电极和衬底之间的电荷存储绝缘层; 在电荷存储绝缘层和衬底之间的隧道绝缘层; 电荷存储绝缘层和控制栅电极之间的阻挡绝缘层; 以及隧道绝缘层和阻挡绝缘层之间的材料层，材料层具有构成势阱底部的能级。

5. 发明申请

US20110079838A1 NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器件
公开(公告)号：US20110079838A1
公开(公告)日：2011-04-07
申请号：US12961678
申请日：2010-12-07
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park , Byeong-In Choe
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park , Byeong-In Choe
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L27/1157 , H01L27/11524 , H01L27/11551 , H01L27/11578 , H01L29/42352 , H01L29/7851 , H01L29/792
摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.
摘要翻译：一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极在栅极结构的相对侧的有源区中的区域。源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。还讨论了相关设备。

6. 发明授权

US07888219B2 Methods of forming charge-trap type non-volatile memory devices 有权
标题翻译：形成电荷陷阱型非易失性存储器件的方法
公开(公告)号：US07888219B2
公开(公告)日：2011-02-15
申请号：US12766272
申请日：2010-04-23
申请人： Jae-Sung Sim , Jung-Dal Choi , Chang-Seok Kang
发明人： Jae-Sung Sim , Jung-Dal Choi , Chang-Seok Kang
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate.
摘要翻译：形成非易失性存储器件的方法可以包括在半导体衬底上形成隧道绝缘层，并在隧道绝缘层上形成电荷捕获层。然后可以形成延伸穿过隧道绝缘层和电荷陷阱层并进入半导体衬底的沟槽，使得电荷陷阱层和隧道绝缘层的部分保留在沟槽的相对侧上。可以在沟槽中形成器件隔离层，并且可以在器件隔离层上和电荷陷阱层的剩余部分上形成阻挡绝缘层。可以在阻挡绝缘层上形成栅电极，并且可以对阻挡绝缘层和电荷陷阱层的剩余部分进行图案化以在栅电极和半导体衬底之间提供阻挡绝缘图案和电荷陷阱图案。

7. 发明授权

US07863676B2 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07863676B2
公开(公告)日：2011-01-04
申请号：US11709814
申请日：2007-02-23
申请人： Sang-Hun Jeon , Jung-Dal Choi , Chang-Seok Kang , Won-Seok Jung
发明人： Sang-Hun Jeon , Jung-Dal Choi , Chang-Seok Kang , Won-Seok Jung
IPC分类号： H01L29/66
CPC分类号： H01L21/823481 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region.
摘要翻译：半导体器件包括在半导体衬底中的器件隔离层，由器件隔离层限定的有源区，包括主表面的有源区和包括低于主表面的底表面的凹陷区，以及栅电极形成在所述凹部区域上，其中，所述器件隔离层的与所述凹部区域相邻的顶面低于所述凹部区域的底面。

8. 发明申请

US20090212340A1 FLASH MEMORY DEVICES 审中-公开
标题翻译：闪存存储器件
公开(公告)号：US20090212340A1
公开(公告)日：2009-08-27
申请号：US12392656
申请日：2009-02-25
申请人： Chang-Hyun Lee , Young-Woo Park , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park
发明人： Chang-Hyun Lee , Young-Woo Park , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L27/11521
摘要： A gate electrode line which extends in a second direction crossing a first direction on a substrate including an active region which is defined by a device isolation layer and extends in the first direction and a charge trap layer disposed between the active region and the gate electrode line, wherein a bottom surface of the gate electrode line disposed on the device isolation layer is lower than a top surface of the charge trap layer disposed on the active region and higher than a top surface of the active region.
摘要翻译：一种栅极电极线，其在包括由器件隔离层限定并在第一方向上延伸的有源区域和设置在有源区域和栅电极线之间的电荷陷阱层的基板上沿与第一方向交叉的第二方向延伸其特征在于，设置在所述器件隔离层上的所述栅电极线的底面低于设置在所述有源区上并高于所述有源区的顶面的所述电荷陷阱层的顶面。

9. 发明申请

US20090001451A1 NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20090001451A1
公开(公告)日：2009-01-01
申请号：US12146653
申请日：2008-06-26
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park , Byeong-In Choe
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park , Byeong-In Choe
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L27/1157 , H01L27/11524 , H01L27/11551 , H01L27/11578 , H01L29/42352 , H01L29/7851 , H01L29/792
摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.
摘要翻译：一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极在栅极结构的相对侧的有源区中的区域。源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。还讨论了相关设备。

10. 发明申请

US20080246073A1 Nonvolatile Memory Devices Including a Resistor Region 审中-公开
标题翻译：包括电阻器区域的非易失性存储器件
公开(公告)号：US20080246073A1
公开(公告)日：2008-10-09
申请号：US12138712
申请日：2008-06-13
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/00
CPC分类号： H01L27/105 , B82Y10/00 , H01L21/823462 , H01L27/0629 , H01L27/11526 , H01L27/11546 , H01L27/11568
摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.
摘要翻译：形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。在电阻器区域中的器件隔离层上形成第一导电层。半导体衬底暴露在电池阵列区域中。电池绝缘层形成在包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的半导体衬底的一部分上。在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

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