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1. 发明授权

US07705621B2 Test pattern and method of monitoring defects using the same 失效
标题翻译：使用相同的测试模式和监测缺陷的方法
公开(公告)号：US07705621B2
公开(公告)日：2010-04-27
申请号：US11852625
申请日：2007-09-10
申请人： Hyock-Jun Lee , Choel-Hwyi Bae , Yeong-Lyeol Park , Nam-Young Lee , Mi-Joung Lee
发明人： Hyock-Jun Lee , Choel-Hwyi Bae , Yeong-Lyeol Park , Nam-Young Lee , Mi-Joung Lee
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , H01L22/34
摘要： A test pattern includes a normal pattern, an abnormal pattern having predetermined defects, and a conductive line electrically connected to the normal pattern and electrically isolated from the abnormal pattern. Thus, a non-contact test process and a contact test process may be compatible with the single test pattern.
摘要翻译：测试图案包括正常图案，具有预定缺陷的异常图案以及与正常图案电连接并与异常图案电隔离的导电线。因此，非接触测试过程和接触测试过程可以与单个测试图案兼容。

2. 发明申请

US20080084223A1 TEST PATTERN AND METHOD OF MONITORING DEFECTS USING THE SAME 失效
标题翻译：测试模式和使用该方法监测缺陷的方法
公开(公告)号：US20080084223A1
公开(公告)日：2008-04-10
申请号：US11852625
申请日：2007-09-10
申请人： Hyock-Jun Lee , Choel-Hwyi Bae , Yeong-Lyeol Park , Nam-Young Lee , Mi-Joung Lee
发明人： Hyock-Jun Lee , Choel-Hwyi Bae , Yeong-Lyeol Park , Nam-Young Lee , Mi-Joung Lee
IPC分类号： G01R31/265
CPC分类号： G01R31/2884 , H01L22/34
摘要： A test pattern includes a normal pattern, an abnormal pattern having predetermined defects, and a conductive line electrically connected to the normal pattern and electrically isolated from the abnormal pattern. Thus, a non-contact test process and a contact test process may be compatible with the single test pattern.
摘要翻译：测试图案包括正常图案，具有预定缺陷的异常图案以及与正常图案电连接并与异常图案电隔离的导电线。因此，非接触测试过程和接触测试过程可以与单个测试图案兼容。

3. 发明申请

US20070296447A1 Monitoring pattern for detecting a defect in a semiconductor device and method for detecting a defect 有权
标题翻译：用于检测半导体器件中的缺陷的监视模式和用于检测缺陷的方法
公开(公告)号：US20070296447A1
公开(公告)日：2007-12-27
申请号：US11798838
申请日：2007-05-17
申请人： Choel-Hwyi Bae , Yong-Woon Han , Mi-Joung Lee , Sang-Deok Kwon
发明人： Choel-Hwyi Bae , Yong-Woon Han , Mi-Joung Lee , Sang-Deok Kwon
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R31/307
摘要： A monitoring pattern for detecting a defect in a semiconductor device allows a voltage contrast inspection which may be verified by an electrical test where no special test pattern is required for the electrical test. The monitoring pattern includes a test pattern with line shapes arranged in parallel and spaced apart at predetermined linewidths and intervals, and an interconnection layer connected to the test pattern, where the test pattern is adapted to be charged with a specific potential to be displayed as a voltage contrast image when scanned with an electron beam.
摘要翻译：用于检测半导体器件中的缺陷的监视模式允许电压对比度检查，其可以通过电测试来验证，其中不需要用于电测试的特殊测试图案。监视图案包括具有平行布置且以预定线宽和间隔间隔开的线形状的测试图案，以及连接到测试图案的互连层，其中测试图案适于以特定电位进行充电以被显示为用电子束扫描时的电压对比度图像。

4. 发明授权

US07733099B2 Monitoring pattern for detecting a defect in a semiconductor device and method for detecting a defect 有权
标题翻译：用于检测半导体器件中的缺陷的监视模式和用于检测缺陷的方法
公开(公告)号：US07733099B2
公开(公告)日：2010-06-08
申请号：US11798838
申请日：2007-05-17
申请人： Choel-Hwyi Bae , Yong-Woon Han , Mi-Joung Lee , Sang-Deok Kwon
发明人： Choel-Hwyi Bae , Yong-Woon Han , Mi-Joung Lee , Sang-Deok Kwon
IPC分类号： G01R31/305 , G01R31/26
CPC分类号： G01R31/2884 , G01R31/307
摘要： A monitoring pattern for detecting a defect in a semiconductor device allows a voltage contrast inspection which may be verified by an electrical test where no special test pattern is required for the electrical test. The monitoring pattern includes a test pattern with line shapes arranged in parallel and spaced apart at predetermined linewidths and intervals, and an interconnection layer connected to the test pattern, where the test pattern is adapted to be charged with a specific potential to be displayed as a voltage contrast image when scanned with an electron beam.
摘要翻译：用于检测半导体器件中的缺陷的监视模式允许电压对比度检查，其可以通过电测试来验证，其中不需要用于电测试的特殊测试图案。监视图案包括具有平行布置且以预定线宽和间隔间隔开的线形状的测试图案，以及连接到测试图案的互连层，其中测试图案适于以特定电位进行充电以被显示为用电子束扫描时的电压对比度图像。

5. 发明申请

US20080250361A1 Method of correcting a design pattern for an integrated circuit and an apparatus for performing the same 有权
标题翻译：校正集成电路的设计图案的方法及其执行装置
公开(公告)号：US20080250361A1
公开(公告)日：2008-10-09
申请号：US12080381
申请日：2008-04-02
申请人： Choel-Hwyi Bae , Jin-Hee Kim , You-Seung Jin , Dong-Hun Lee
发明人： Choel-Hwyi Bae , Jin-Hee Kim , You-Seung Jin , Dong-Hun Lee
IPC分类号： G06F17/50
CPC分类号： G03F1/72
摘要： In an apparatus and method for automatically correcting a design pattern in view of different process defects, defect characteristic functions that indicate frequencies of each process defect independent from one another are generated, and a normalization factor that indicates relationships between the defect characteristic functions is determined. A general defect characteristic function indicating a frequency of general defects is generated using the defect characteristic functions and the normalization factor. The general defect causes the same process failure as caused by each of the process defects. The design pattern is modified using the general defect characteristic function in such a manner that the frequency of the general defects is minimized when at least one portion of the design pattern corresponding to the model pattern is transcribed on the substrate. Accordingly, the whole design pattern may be automatically corrected based on the general defect characteristic function.
摘要翻译：在用于根据不同的工艺缺陷自动校正设计图案的装置和方法中，生成指示彼此独立的每个处理缺陷的频率的缺陷特征函数，并且确定指示缺陷特征函数之间的关系的归一化因子。使用缺陷特征函数和归一化因子生成表示一般缺陷频率的一般缺陷特征函数。一般缺陷导致由每个工艺缺陷引起的相同的过程故障。使用一般缺陷特征函数修改设计图案，使得当在衬底上转录对应于模型图案的设计图案的至少一部分时，一般缺陷的频率最小化。因此，可以基于一般缺陷特征函数自动校正整个设计图案。

6. 发明申请

US20080224134A1 Test Structures for Identifying an Allowable Process Margin for Integrated Circuits and Related Methods 有权
标题翻译：用于识别集成电路允许过程保证金的测试结构及相关方法
公开(公告)号：US20080224134A1
公开(公告)日：2008-09-18
申请号：US12046065
申请日：2008-03-11
申请人： Choel-Hwyi Bae , You-Seung Jin
发明人： Choel-Hwyi Bae , You-Seung Jin
IPC分类号： H01L23/544 , H01L21/66
CPC分类号： H01L22/34
摘要： A test structure for inspecting an allowable process margin in a manufacturing process for a semiconductor device is provided. The test structure includes a plurality of grounded conductive lines on a substrate and electrically grounded to the substrate. A plurality of floating conductive lines are provided, each of the plurality of conductive lines being spaced apart from the grounded conductive lines and electrically separated from the grounded conductive lines on the substrate. A plurality of supplementary patterns are provided for measuring the allowable process margin by a voltage contrast between the grounded conductive lines and the floating conductive lines. Related methods of testing are also provided.
摘要翻译：提供了一种用于在半导体器件的制造工艺中检查允许工艺余量的测试结构。测试结构包括在基板上的多个接地导线并且电接地到基板。提供多条浮动导线，多条导线中的每条导线与接地的导线间隔开，并与衬底上的接地导线电隔离。提供多个补充图案，用于通过接地导线与浮动导线之间的电压对比度来测量允许的工艺余量。还提供了相关的测试方法。

7. 发明授权

US07642106B2 Methods for identifying an allowable process margin for integrated circuits 有权
标题翻译：识别集成电路允许的工艺余量的方法
公开(公告)号：US07642106B2
公开(公告)日：2010-01-05
申请号：US12046065
申请日：2008-03-11
申请人： Choel-Hwyi Bae , You-Seung Jin
发明人： Choel-Hwyi Bae , You-Seung Jin
IPC分类号： H01L21/66
CPC分类号： H01L22/34
摘要： A test structure for inspecting an allowable process margin in a manufacturing process for a semiconductor device is provided. The test structure includes a plurality of grounded conductive lines on a substrate and electrically grounded to the substrate. A plurality of floating conductive lines are provided, each of the plurality of conductive lines being spaced apart from the grounded conductive lines and electrically separated from the grounded conductive lines on the substrate. A plurality of supplementary patterns are provided for measuring the allowable process margin by a voltage contrast between the grounded conductive lines and the floating conductive lines. Related methods of testing are also provided.
摘要翻译：提供了一种用于在半导体器件的制造工艺中检查允许工艺余量的测试结构。测试结构包括在基板上的多个接地导线并且电接地到基板。提供多条浮动导线，多条导线中的每条导线与接地的导线间隔开，并与衬底上的接地导线电隔离。提供多个补充图案，用于通过接地导线与浮动导线之间的电压对比度来测量允许的工艺余量。还提供了相关的测试方法。

8. 发明授权

US07840917B2 Method of correcting a design pattern for an integrated circuit and an apparatus for performing the same 有权
标题翻译：校正集成电路的设计图案的方法及其执行装置
公开(公告)号：US07840917B2
公开(公告)日：2010-11-23
申请号：US12080381
申请日：2008-04-02
申请人： Choel-Hwyi Bae , Jin-Hee Kim , You-Seung Jin , Dong-Hun Lee
发明人： Choel-Hwyi Bae , Jin-Hee Kim , You-Seung Jin , Dong-Hun Lee
IPC分类号： G06F17/50
CPC分类号： G03F1/72
摘要： In an apparatus and method for automatically correcting a design pattern in view of different process defects, defect characteristic functions that indicate frequencies of each process defect independent from one another are generated, and a normalization factor that indicates relationships between the defect characteristic functions is determined. A general defect characteristic function indicating a frequency of general defects is generated using the defect characteristic functions and the normalization factor. The general defect causes the same process failure as caused by each of the process defects. The design pattern is modified using the general defect characteristic function in such a manner that the frequency of the general defects is minimized when at least one portion of the design pattern corresponding to the model pattern is transcribed on the substrate. Accordingly, the whole design pattern may be automatically corrected based on the general defect characteristic function.
摘要翻译：在用于根据不同的工艺缺陷自动校正设计图案的装置和方法中，生成指示彼此独立的各过程缺陷的频率的缺陷特征函数，并且确定指示缺陷特征函数之间的关系的归一化因子。使用缺陷特征函数和归一化因子生成表示一般缺陷频率的一般缺陷特征函数。一般缺陷导致由每个工艺缺陷引起的相同的过程故障。使用一般缺陷特征函数修改设计图案，使得当在衬底上转录对应于模型图案的设计图案的至少一部分时，一般缺陷的频率最小化。因此，可以基于一般缺陷特征函数自动校正整个设计图案。

9. 发明授权

US07802210B2 Methods and systems for analyzing layouts of semiconductor integrated circuit devices 有权
标题翻译：分析半导体集成电路器件布局的方法和系统
公开(公告)号：US07802210B2
公开(公告)日：2010-09-21
申请号：US11654340
申请日：2007-01-17
申请人： Choel-Hwyi Bae , Gwang-Hyeon Baek , Min-Geon Cho
发明人： Choel-Hwyi Bae , Gwang-Hyeon Baek , Min-Geon Cho
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Disclosed is a method of analyzing layouts of semiconductor integrated circuit devices. The method includes calculating random fault rates, systematic fault rates, parametric fault rates, and areas of a plurality of layouts of interest; calculating area-based fault rates of the plurality of layouts of interest using the random fault rate, systematic fault rate, parametric fault rate, and area; and selecting layouts of interest to be corrected from among the plurality of layouts of interest using the area-based fault rates of the plurality of layouts of interest.
摘要翻译：公开了分析半导体集成电路器件的布局的方法。该方法包括计算随机故障率，系统故障率，参数故障率和感兴趣的多个布局的区域; 使用随机故障率，系统故障率，参数故障率和面积来计算多个感兴趣布局的基于区域的故障率; 以及使用感兴趣的多个布局的基于区域的故障率从感兴趣的多个布局中选择要校正的兴趣的布局。

10. 发明申请

US20070174800A1 Methods and systems for analyzing layouts of semiconductor integrated circuit devices 有权
标题翻译：分析半导体集成电路器件布局的方法和系统
公开(公告)号：US20070174800A1
公开(公告)日：2007-07-26
申请号：US11654340
申请日：2007-01-17
申请人： Choel-Hwyi Bae , Gwang-Hyeon Baek , Min-Geon Cho
发明人： Choel-Hwyi Bae , Gwang-Hyeon Baek , Min-Geon Cho
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Disclosed is a method of analyzing layouts of semiconductor integrated circuit devices. The method includes calculating random fault rates, systematic fault rates, parametric fault rates, and areas of a plurality of layouts of interest; calculating area-based fault rates of the plurality of layouts of interest using the random fault rate, systematic fault rate, parametric fault rate, and area; and selecting layouts of interest to be corrected from among the plurality of layouts of interest using the area-based fault rates of the plurality of layouts of interest.
摘要翻译：公开了分析半导体集成电路器件的布局的方法。该方法包括计算随机故障率，系统故障率，参数故障率和感兴趣的多个布局的区域; 使用随机故障率，系统故障率，参数故障率和面积来计算多个感兴趣布局的基于区域的故障率; 以及使用感兴趣的多个布局的基于区域的故障率从感兴趣的多个布局中选择要校正的兴趣的布局。

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