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    • 6. 发明申请
    • DEVICE AND METHOD GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE
    • 在半导体存储器件中产生内部电压的器件和方法
    • US20090207674A1
    • 2009-08-20
    • US12372290
    • 2009-02-17
    • Soo-Bong ChangDoo-Young KimJung-Im Huh
    • Soo-Bong ChangDoo-Young KimJung-Im Huh
    • G11C7/00G11C5/14
    • G11C5/147
    • A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.
    • 提供半导体存储器件和在半导体存储器件中产生内部电压的方法。 半导体存储器件包括:控制器,被配置为当从外部施加有效命令时激活感测使能信号,当施加预充电命令时使感测使能信号失效,并输出感测使能信号;以及阵列内部电压发生器,被配置为 当感测使能信号被激活时,输出有源阵列电源电压作为阵列电源电压,当感测使能信号被去激活时,输出外部阵列电源电压和备用阵列电源电压作为阵列电源电压;以及 当感测使能信号在至少特定的时间段内被去激活时,单独输出备用阵列电源电压作为阵列电源电压。
    • 7. 发明授权
    • Circuit and method for generating word line control signals and semiconductor memory device having the same
    • 用于产生字线控制信号的电路和方法以及具有该字线控制信号的半导体存储器件
    • US07206252B2
    • 2007-04-17
    • US11141783
    • 2005-05-31
    • Doo-Young Kim
    • Doo-Young Kim
    • G11C8/00
    • G11C8/10
    • A circuit for generating word line control signals that have a stable boosting margin of the sub-word line driver: The circuit includes a first address buffer, a pre-decoder unit, a second address buffer, a main decoder and a circuit for generating a word-line boosting signal. The second address buffer delays a refresh count signal for a predetermined time and generates an enable signal having a predetermined pulse width in response to a row address setup signal and the delayed refresh count signal, and receives and latches a pre-decoded row address signals to output decoded row address signals in response to the enable signal. Accordingly, the circuit for generating word line control signals is capable of obtaining a stable self-boosting margin when the semiconductor memory device operates in a refresh mode.
    • 一种用于产生具有所述子字线驱动器的稳定升压裕度的字线控制信号的电路:所述电路包括第一地址缓冲器,预解码器单元,第二地址缓冲器,主解码器和用于产生 字线升压信号。 第二地址缓冲器将刷新计数信号延迟预定时间,并且响应于行地址建立信号和延迟刷新计数信号产生具有预定脉冲宽度的使能信号,并且接收并锁存预解码的行地址信号 响应于使能信号输出解码的行地址信号。 因此,当半导体存储器件以刷新模式工作时,用于产生字线控制信号的电路能够获得稳定的自增益裕度。
    • 10. 发明申请
    • DEVICE AND METHOD GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE
    • 在半导体存储器件中产生内部电压的器件和方法
    • US20120213018A1
    • 2012-08-23
    • US13462915
    • 2012-05-03
    • Soo-Bong ChangDoo-Young KimJung-Im Huh
    • Soo-Bong ChangDoo-Young KimJung-Im Huh
    • G11C7/00
    • G11C5/147
    • A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.
    • 提供半导体存储器件和在半导体存储器件中产生内部电压的方法。 半导体存储器件包括:控制器,被配置为当从外部施加有效命令时激活感测使能信号,当施加预充电命令时使感测使能信号失效,并输出感测使能信号;以及阵列内部电压发生器,被配置为 当感测使能信号被激活时,输出有源阵列电源电压作为阵列电源电压,当感测使能信号被去激活时,输出外部阵列电源电压和备用阵列电源电压作为阵列电源电压;以及 当感测使能信号在至少特定的时间段内被去激活时,单独输出备用阵列电源电压作为阵列电源电压。