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1. 发明授权

US06232183B1 Method for fabricating a flash memory 有权
标题翻译：制造闪存的方法
公开(公告)号：US06232183B1
公开(公告)日：2001-05-15
申请号：US09227680
申请日：1999-01-08
申请人： Hwi-Huang Chen , Wenchi Ting
发明人： Hwi-Huang Chen , Wenchi Ting
IPC分类号： H01L21336
CPC分类号： H01L29/66825
摘要： A method for fabricating a flash memory is disclosed, in which a stacked gate structure comprising a floating gate and a control gate on the substrate is first formed. Ions are implanted into the substrate at one side of the stacked gate. A drain having a heavily doped region and a lightly doped region are subsequently formed. Spacers one each side of the stacked gate structure are formed. By using a photoresist layer covering the spacer at the drain end, the spacer at the source end can be reduced by an etching process. The source region of the flash memory is formed by implanting ions into the substrate using the reduced spacer as a mask.
摘要翻译：公开了一种用于制造闪速存储器的方法，其中首先形成包括浮置栅极和基板上的控制栅极的堆叠栅极结构。离子在堆叠栅极的一侧被植入衬底中。随后形成具有重掺杂区和轻掺杂区的漏极。形成堆叠栅极结构的每一侧的间隔。通过使用在漏极端覆盖间隔物的光致抗蚀剂层，通过蚀刻工艺可以减少源极处的间隔物。通过使用还原间隔物作为掩模将离子注入到衬底中来形成闪存的源区。

2. 发明授权

US08420488B2 Method of fabricating high voltage device 有权
标题翻译：制造高压器件的方法
公开(公告)号：US08420488B2
公开(公告)日：2013-04-16
申请号：US11853499
申请日：2007-09-11
申请人： Yun-Han Ma , Ming-Tsung Lee , Shih-Ming Liang , Hwi-Huang Chen
发明人： Yun-Han Ma , Ming-Tsung Lee , Shih-Ming Liang , Hwi-Huang Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/513 , H01L21/28167 , H01L29/0653 , H01L29/4908
摘要： A high voltage device is provided. The high voltage device includes a gate on a substrate, two source/drain regions in the substrate beside the gate, and a composite gate dielectric layer that includes at least two stacked continuous layers, extending from one side to another side of the gate. Wherein, the at least two stacked continuous layers is a combination of at least one thermal oxide layer and at least one chemical vapor deposited layer.
摘要翻译：提供高压装置。高电压器件包括衬底上的栅极，栅极旁边的衬底中的两个源极/漏极区域和复合栅极电介质层，其包括从栅极的一侧延伸到另一侧的至少两个层叠的连续层。其中，所述至少两个堆叠的连续层是至少一个热氧化物层和至少一个化学气相沉积层的组合。

3. 发明申请

US20070018258A1 High-Voltage Device Structure 有权
标题翻译：高压器件结构
公开(公告)号：US20070018258A1
公开(公告)日：2007-01-25
申请号：US11160657
申请日：2005-07-05
申请人： Anchor Chen , Chih-Hung Lin , Hwi-Huang Chen , Jih-Wei Liou , Chin-Hung Liu , Ming-Tsung Tung , Chien-Ming Lin , Jung-Ching CHEN
发明人： Anchor Chen , Chih-Hung Lin , Hwi-Huang Chen , Jih-Wei Liou , Chin-Hung Liu , Ming-Tsung Tung , Chien-Ming Lin , Jung-Ching CHEN
IPC分类号： H01L29/76
CPC分类号： H01L29/0692 , H01L29/0638 , H01L29/1041 , H01L29/7833
摘要： A high-voltage device structure includes a high-voltage device disposed on a semiconductor substrate. The semiconductor includes an active region and an isolation region, and the high-voltage device is disposed in the active region. The high-voltage device structure includes a source diffusion region of a first conductive type, a drain region of the first conductive type, and a gate longer than the source diffusion region and the drain diffusion region so as to form spare regions on both sides of the gate. The isolation region is outside the active region and surrounds the active region. In the isolation region, an isolation ion implantation region of a second conductive type and an extended ion implantation region are disposed to prevent parasitic current from being generating between the source diffusion region and the drain diffusion region.
摘要翻译：高压器件结构包括设置在半导体衬底上的高电压器件。半导体包括有源区和隔离区，高压器件设置在有源区中。高压器件结构包括第一导电类型的源极扩散区域，第一导电类型的漏极区域和比源极扩散区域和漏极扩散区域更长的栅极，以在第二导电类型的两侧形成备用区域大门。隔离区域在有源区域之外并且围绕有源区域。在隔离区域中，设置第二导电型隔离离子注入区域和延伸离子注入区域，以防止在源极扩散区域和漏极扩散区域之间产生寄生电流。

4. 发明授权

US5882970A Method for fabricating flash memory cell having a decreased overlapped region between its source and gate 失效
标题翻译：一种用于制造其源极和栅极之间具有减小的重叠区域的闪存单元的方法
公开(公告)号：US5882970A
公开(公告)日：1999-03-16
申请号：US552428
申请日：1995-11-03
申请人： Chih-Hung Lin , Hwi-Huang Chen , Gary Hong , Chen-Chiu Hsue
发明人： Chih-Hung Lin , Hwi-Huang Chen , Gary Hong , Chen-Chiu Hsue
IPC分类号： H01L21/336 , H01L21/8247
CPC分类号： H01L29/66825
摘要： A flash memory cell is fabricated by forming a lightly-doped region with only an implantation procedure to avoid lateral diffusion resulting from an increased overlap between the source region and gate as well as a short channel effect, while surrounding the source region with the lightly-doped region to thereby increase the breakdown voltage between the source region and the substrate.
摘要翻译：闪存单元是通过仅通过注入步骤形成轻掺杂区域来制造的，以避免由于源区和栅极之间的重叠增加而产生的横向扩散以及短沟道效应，同时围绕源极区域，从而增加源极区域和衬底之间的击穿电压。

5. 发明授权

US5700708A Process for fabricating storage capacitor for DRAM memory cell 失效
标题翻译：制造用于DRAM存储单元的存储电容器的工艺
公开(公告)号：US5700708A
公开(公告)日：1997-12-23
申请号：US665386
申请日：1996-06-18
申请人： Hwi-Huang Chen , Gary Hong
发明人： Hwi-Huang Chen , Gary Hong
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A process for fabricating a storage capacitor for memory cell units of a DRAM memory device to achieve an increased capacitance value. The process includes first forming a transistor including a gate, a source region, and a drain region on the silicon substrate of the device. The gate includes a first polysilicon layer covered by an insulating layer. A silicon nitride layer is formed covering the transistor and a silicon oxide layer is formed on the silicon nitride layer. A contact opening is formed in the silicon oxide layer and the silicon nitride layer which exposes the surface of the transistor drain/source region. The silicon oxide layer has an edge portion extending toward the cavity of the contact opening more than the edge of the silicon nitride layer below it extends. A second polysilicon layer is then formed in the contact opening, covering the exposed drain region, the gate, and the edge portion of the silicon oxide layer and the silicon nitride layer. The second polysilicon layer thus provides the first electrode of the storage capacitor. A dielectric layer is formed on the second polysilicon layer to provide the dielectric of the storage capacitor and a third polysilicon layer is formed on the dielectric layer to provide the second electrode of the storage capacitor.
摘要翻译：一种用于制造DRAM存储器件的存储单元单元的存储电容器以实现增加的电容值的过程。该工艺包括首先在器件的硅衬底上形成包括栅极，源极区和漏极区的晶体管。栅极包括被绝缘层覆盖的第一多晶硅层。形成覆盖晶体管的氮化硅层，并且在氮化硅层上形成氧化硅层。在氧化硅层和暴露晶体管漏极/源极区域的表面的氮化硅层上形成接触开口。氧化硅层具有比其延伸的氮化硅层的边缘朝向接触开口的空腔延伸的边缘部分。然后在接触开口中形成第二多晶硅层，覆盖暴露的漏极区域，栅极以及氧化硅层和氮化硅层的边缘部分。因此，第二多晶硅层提供存储电容器的第一电极。在第二多晶硅层上形成电介质层以提供存储电容器的电介质，并且在电介质层上形成第三多晶硅层以提供存储电容器的第二电极。

6. 发明授权

US5506167A Method of making a high resistance drain junction resistor in a SRAM 失效
标题翻译：在SRAM中制作高电阻漏极结电阻的方法
公开(公告)号：US5506167A
公开(公告)日：1996-04-09
申请号：US421000
申请日：1995-04-13
申请人： Hwi-Huang Chen , Gary Hong
发明人： Hwi-Huang Chen , Gary Hong
IPC分类号： H01L27/11 , H01L21/70
CPC分类号： H01L27/1112 , Y10S438/934
摘要： An improved SRAM resistor structure having implanted therein ions of an material in the surface layer of a drain junction region juxtaposed to an overlying metal contact layer providing the benefits of high resistance, low energy consumption, a single ion implantation step in an easily controlled process while producing a precise resistance desired and a method of making the SRAM resistor structure.
摘要翻译：一种改进的SRAM电阻器结构，其中注入了与上覆金属接触层并列的漏极结区域的表面层中的材料的离子，提供了高电阻，低能耗的优点，易于控制的过程中的单一离子注入步骤，产生所需的精确电阻和制造SRAM电阻器结构的方法。

7. 发明申请

US20140266418A1 Stacked Chip System 有权
标题翻译：堆叠芯片系统
公开(公告)号：US20140266418A1
公开(公告)日：2014-09-18
申请号：US13835055
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/50
CPC分类号： H01L23/50 , H01L23/481 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.
摘要翻译：提供堆叠式芯片系统以包括第一芯片，第二芯片，连接第一芯片和第二芯片的第一组直通硅通孔（TSV），并且包括至少一个第一VSS TSV，至少一个第一VDD TSV，多个第一信号TSV和连接第一芯片和第二芯片的至少一个第一冗余TSV和第二组穿通硅通孔（TSV），并且包括至少一个第二VSS TSV，至少一个第二VDD TSV，多个第二信号TSV和至少一个第二冗余TSV，其中所有所述第一组TSV由被配置为选择所述至少一个第一冗余TSV并绕过所述第一组TSV的其余部分中的至少一个的第一选择电路耦合，以及其中所述至少一个第一冗余TSV和所述至少第二冗余TSV由被配置为允许它们中的一个替换另一个的第二选择电路耦合。

8. 发明申请

US20140264869A1 Semiconductor Device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20140264869A1
公开(公告)日：2014-09-18
申请号：US13834806
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/532 , H01L23/522
CPC分类号： H01L23/53238 , H01L21/76847 , H01L23/481 , H01L24/05 , H01L24/06 , H01L2224/02331 , H01L2224/02372 , H01L2224/0401 , H01L2224/05008 , H01L2224/05023 , H01L2224/05025 , H01L2224/05147 , H01L2224/05149 , H01L2224/05166 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05548 , H01L2224/05568 , H01L2224/05582 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/06181 , H01L2224/1134 , H01L2924/00014 , H01L2924/04941 , H01L2924/04953
摘要： A semiconductor device comprises a substrate having a first side with a first surface and a second side with a second surface, a recessed through silicon via (TSV) penetrating the substrate and forming a first step height with respect to the first surface of the first side, a first extruded backside redistribution line (RDL) filling in the first step height and engaging with the recessed through silicon via.
摘要翻译：半导体器件包括具有第一表面和第二表面的第一侧面的衬底，穿过衬底的凹入的硅通孔（TSV），并相对于第一侧面的第一表面形成第一台阶高度，第一挤压后侧再分配线（RDL），其填充在第一级高度并与凹进的硅通孔接合。

9. 发明授权

US06268241B1 Method of forming a self-aligned silicide structure in integrated circuit fabrication 失效
标题翻译：在集成电路制造中形成自对准硅化物结构的方法
公开(公告)号：US06268241B1
公开(公告)日：2001-07-31
申请号：US09408152
申请日：1999-09-29
申请人： Hwi-Huang Chen , Gary Hong
发明人： Hwi-Huang Chen , Gary Hong
IPC分类号： H01L218249
CPC分类号： H01L21/28052 , H01L29/665
摘要： A method for forming a self-aligned silicide (or called salicide) structure in IC fabrication is described. This method is characterized by the step of making the top surface of a polysilicon-based structure into a rugged surface, which allows the subsequently formed salicide structure over the rugged surface of the polysilicon-based structure to have an increased surface area and thus have a reduced sheet resistance when compared to the prior art. By this method, the first step is to prepare a semiconductor substrate, after which an oxide layer is formed over the substrate. Next, a polysilicon-based structure is formed over the oxide layer, and then the exposed surface of the polysilicon-based structure is reshaped into a rugged surface. Subsequently, a silicide layer is formed over the rugged surface of the polysilicon-based structure, which serves as the intended salicide structure.
摘要翻译：描述了在IC制造中形成自对准硅化物（或称为自对准硅化物）结构的方法。该方法的特征在于使基于多晶硅的结构的顶表面成为粗糙表面的步骤，其允许在多晶硅基结构的粗糙表面上随后形成的自对准硅化物结构具有增加的表面积，因此具有与现有技术相比降低了薄层电阻。通过该方法，第一步是制备半导体衬底，然后在衬底上形成氧化物层。接下来，在氧化物层上形成多晶硅基结构，然后将多晶硅基结构的暴露表面重新成形为粗糙的表面。随后，在多晶硅基结构的粗糙表面上形成硅化物层，其用作预期的自对准硅化物结构。

10. 发明授权

US06235582B1 Method for forming flash memory cell 有权
标题翻译：形成闪存单元的方法
公开(公告)号：US06235582B1
公开(公告)日：2001-05-22
申请号：US09223613
申请日：1998-12-30
申请人： Hwi-Huang Chen
发明人： Hwi-Huang Chen
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , H01L29/42324
摘要： A method for forming a flash memory cell forms an insulating layer on a provided substrate and a number of openings are formed within the insulating layer to expose the substrate. A patterned conductive layer having a dopant is formed and fills the openings on the substrate. By driving the dopant into the substrate, source/drain regions are formed. A gate structure is formed on a channel region between the source/drain regions to accomplish the flash memory cell.
摘要翻译：形成闪存单元的方法在所提供的衬底上形成绝缘层，并且在绝缘层内形成多个开口以露出衬底。形成具有掺杂剂的图案化导电层并填充衬底上的开口。通过将掺杂剂驱动到衬底中，形成源/漏区。栅极结构形成在源/漏区之间的沟道区上，以完成闪存单元。

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