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1. 发明授权

US08225150B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08225150B2
公开(公告)日：2012-07-17
申请号：US13149683
申请日：2011-05-31
申请人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
发明人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
IPC分类号： G11C29/00 , G01R31/28 , H03M13/00
CPC分类号： G11C29/12 , G11C11/401
摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.
摘要翻译：半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元执行包括写入操作的多个内部操作来检测缺陷在晶圆级别。

2. 发明申请

US20090219775A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20090219775A1
公开(公告)日：2009-09-03
申请号：US12154870
申请日：2008-05-28
申请人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
发明人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
IPC分类号： G11C29/00 , G11C7/00 , G11C8/00
CPC分类号： G11C29/12 , G11C11/401
摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.
摘要翻译：半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元执行包括写入操作的多个内部操作来检测缺陷在晶圆级别。

3. 发明申请

US20110231717A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110231717A1
公开(公告)日：2011-09-22
申请号：US13149683
申请日：2011-05-31
申请人： Hwang HUR , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
发明人： Hwang HUR , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G11C29/12 , G11C11/401
摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.
摘要翻译：半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元来执行包括写入操作的多个内部操作来检测缺陷在晶圆级别。

4. 发明授权

US07979758B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07979758B2
公开(公告)日：2011-07-12
申请号：US12154870
申请日：2008-05-28
申请人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
发明人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/12 , G11C11/401
摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.
摘要翻译：半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元执行包括写入操作的多个内部操作来检测缺陷在晶圆级别。

5. 发明申请

US20100169583A1 MULTI-PORT MEMORY DEVICE WITH SERIAL INPUT/OUTPUT INTERFACE 有权
标题翻译：具有串行输入/输出接口的多端口存储器件
公开(公告)号：US20100169583A1
公开(公告)日：2010-07-01
申请号：US12717011
申请日：2010-03-03
申请人： Jin-Il Chung , Jae-II Kim , Chang-Ho Do , Hwang Hur
发明人： Jin-Il Chung , Jae-II Kim , Chang-Ho Do , Hwang Hur
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C7/22 , G11C7/222 , G11C8/16 , G11C29/26 , G11C29/32
摘要： A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks.
摘要翻译：多端口存储器件包括端口，存储体，全局数据总线，输入/输出（I / O）控制器，模式寄存器集（MRS），时钟发生器和测试I / O控制器。 I / O控制器响应于模式寄存器使能信号将测试信号发送到全局数据总线。 MRS响应于模式寄存器使能信号产生测试使能信号，并输出一个模式选择信号，该模式选择信号响应于测试信号确定测试I / O信号的数据传输模式。时钟发生器响应于模式选择信号接收外部时钟并基于外部时钟生成内部时钟。测试I / O控制器与内部时钟同步输入/输出测试I / O信号。在测试操作模式期间模式寄存器使能信号有效，用于测试存储体的核心区域。

6. 发明授权

US08031552B2 Multi-port memory device with serial input/output interface 有权
标题翻译：具有串行输入/输出接口的多端口存储器件
公开(公告)号：US08031552B2
公开(公告)日：2011-10-04
申请号：US12717011
申请日：2010-03-03
申请人： Jin-Il Chung , Jae-Il Kim , Chang-Ho Do , Hwang Hur
发明人： Jin-Il Chung , Jae-Il Kim , Chang-Ho Do , Hwang Hur
IPC分类号： G11C8/00
CPC分类号： G11C7/1075 , G11C7/22 , G11C7/222 , G11C8/16 , G11C29/26 , G11C29/32
摘要： A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks.
摘要翻译：多端口存储器件包括端口，存储体，全局数据总线，输入/输出（I / O）控制器，模式寄存器集（MRS），时钟发生器和测试I / O控制器。 I / O控制器响应于模式寄存器使能信号将测试信号发送到全局数据总线。 MRS响应于模式寄存器使能信号产生测试使能信号，并输出一个模式选择信号，该模式选择信号响应于测试信号确定测试I / O信号的数据传输模式。时钟发生器响应于模式选择信号接收外部时钟并基于外部时钟生成内部时钟。测试I / O控制器与内部时钟同步输入/输出测试I / O信号。在测试操作模式期间模式寄存器使能信号有效，用于测试存储体的核心区域。

7. 发明授权

US07701800B2 Multi-port memory device with serial input/output interface 有权
标题翻译：具有串行输入/输出接口的多端口存储器件
公开(公告)号：US07701800B2
公开(公告)日：2010-04-20
申请号：US11824440
申请日：2007-06-29
申请人： Jin-Il Chung , Jae-Il Kim , Chang-Ho Do , Hwang Hur
发明人： Jin-Il Chung , Jae-Il Kim , Chang-Ho Do , Hwang Hur
IPC分类号： G11C8/00
CPC分类号： G11C7/1075 , G11C7/22 , G11C7/222 , G11C8/16 , G11C29/26 , G11C29/32
摘要： A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks.
摘要翻译：多端口存储器件包括端口，存储体，全局数据总线，输入/输出（I / O）控制器，模式寄存器集（MRS），时钟发生器和测试I / O控制器。 I / O控制器响应于模式寄存器使能信号将测试信号发送到全局数据总线。 MRS响应于模式寄存器使能信号产生测试使能信号，并输出一个模式选择信号，该模式选择信号响应于测试信号确定测试I / O信号的数据传输模式。时钟发生器响应于模式选择信号接收外部时钟并基于外部时钟生成内部时钟。测试I / O控制器与内部时钟同步输入/输出测试I / O信号。在测试操作模式期间模式寄存器使能信号有效，用于测试存储体的核心区域。

8. 发明申请

US20080005493A1 Multi-port memory device with serial input/output interface 有权
标题翻译：具有串行输入/输出接口的多端口存储器件
公开(公告)号：US20080005493A1
公开(公告)日：2008-01-03
申请号：US11824440
申请日：2007-06-29
申请人： Jin-Il Chung , Jae-Il Kim , Chang-Ho Do , Hwang Hur
发明人： Jin-Il Chung , Jae-Il Kim , Chang-Ho Do , Hwang Hur
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C7/22 , G11C7/222 , G11C8/16 , G11C29/26 , G11C29/32
摘要： A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks.
摘要翻译：多端口存储器件包括端口，存储体，全局数据总线，输入/输出（I / O）控制器，模式寄存器组（MRS），时钟发生器和测试I / O控制器。 I / O控制器响应于模式寄存器使能信号将测试信号发送到全局数据总线。 MRS响应于模式寄存器使能信号产生测试使能信号，并输出一个模式选择信号，该模式选择信号响应于测试信号确定测试I / O信号的数据传输模式。时钟发生器响应于模式选择信号接收外部时钟并基于外部时钟生成内部时钟。测试I / O控制器与内部时钟同步输入/输出测试I / O信号。在测试操作模式期间模式寄存器使能信号有效，用于测试存储体的核心区域。

9. 发明授权

US07660168B2 Read operation of multi-port memory device 有权
标题翻译：多端口存储设备的读操作
公开(公告)号：US07660168B2
公开(公告)日：2010-02-09
申请号：US11903170
申请日：2007-09-20
申请人： Jae-Il Kim , Chang-Ho Do , Jin-Il Chung , Jae-Hyuk Im
发明人： Jae-Il Kim , Chang-Ho Do , Jin-Il Chung , Jae-Hyuk Im
IPC分类号： G11C16/04
CPC分类号： G11C7/1075 , G11C7/1039 , G11C7/18 , G11C7/22 , G11C7/222 , G11C8/16 , G11C2207/108
摘要： A multi-port memory device includes a plurality of ports, a plurality of bank control units, a plurality of banks, a read clock generation unit, and a data transmission unit. Each of the banks is connected to a corresponding one of the bank control units. The read clock generation unit generates a read clock toggling for four clocks in response to a read command. The data transmission unit transmits a read data from the banks to a corresponding one of the ports in response to the read clock. Every bank control unit is connected to all of the ports.
摘要翻译：多端口存储器件包括多个端口，多个存储体控制单元，多个存储体，读时钟生成单元和数据传输单元。每个银行都连接到相应的一个银行控制单元。读取时钟生成单元响应于读取命令产生四个时钟的读取时钟。数据传输单元响应于读时钟将读取的数据从存储体发送到对应的一个端口。每个银行控制单元连接到所有端口。

10. 发明申请

US20090302913A1 CIRCUIT AND METHOD FOR INITIALIZING AN INTERNAL LOGIC UNIT IN A SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：用于在半导体存储器件中初始化内部逻辑单元的电路和方法
公开(公告)号：US20090302913A1
公开(公告)日：2009-12-10
申请号：US12541102
申请日：2009-08-13
申请人： Jin-Il Chung , Chang-Ho Do
发明人： Jin-Il Chung , Chang-Ho Do
IPC分类号： H03K3/02
CPC分类号： H03K3/0375
摘要： Provided is a semiconductor memory device and a driving method for initializing an internal logic circuit within the semiconductor memory device under a stable state of a source voltage without an extra reset pin. The semiconductor memory device includes a power-up signal generating unit for generating a power-up signal; an internal reset signal generating unit for generating an internal reset signal in response to a pad signal inputted from an arbitrary external pin during a test mode; an internal logic initializing signal generating unit for generating an internal logic initializing signal based on the power-up signal and the internal reset signal; and an internal logic unit initialized in response to the internal logic initializing signal.
摘要翻译：提供一种半导体存储器件和驱动方法，用于在源极电压的稳定状态下初始化半导体存储器件内部的内部逻辑电路，而不需要额外的复位引脚。半导体存储器件包括用于产生上电信号的上电信号产生单元; 内部复位信号产生单元，用于响应于在测试模式期间从任意外部引脚输入的焊盘信号产生内部复位信号; 内部逻辑初始化信号生成单元，用于基于所述上电信号和所述内部复位信号生成内部逻辑初始化信号; 以及响应于内部逻辑初始化信号而初始化的内部逻辑单元。

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