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1. 发明授权

US08638137B2 Delay locked loop 有权
标题翻译：延迟锁定环路
公开(公告)号：US08638137B2
公开(公告)日：2014-01-28
申请号：US13448547
申请日：2012-04-17
申请人： Jin Il Chung
发明人： Jin Il Chung
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： A semiconductor device includes a delay unit configured to delay an inputted clock to generate a delay clock, a selection unit configured to select and output one of the inputted clock and the delay clock, a delay locked loop configured to perform a delay locking operation using a signal delivered from the selection unit, and a selection control unit configured to control the selection unit in response to a comparison of one period of the inputted clock and a maximum delay value of the delay locked loop.
摘要翻译：半导体器件包括：延迟单元，被配置为延迟输入的时钟以产生延迟时钟;选择单元，被配置为选择并输出所输入的时钟和所述延迟时钟中的一个;延迟锁定环，被配置为使用从所述选择单元传送的信号;以及选择控制单元，被配置为响应于所述输入时钟的一个周期与所述延迟锁定环的最大延迟值的比较来控制所述选择单元。

2. 发明申请

US20130156126A1 RAIL-TO-RAIL COMPARATOR, PULSE AMPLITUDE MODULATION RECEIVER, AND COMMUNICATION SYSTEM USING THE SAME 有权
标题翻译：轨至轨比较器，脉冲振幅调制接收器和使用该通信系统的通信系统
公开(公告)号：US20130156126A1
公开(公告)日：2013-06-20
申请号：US13590282
申请日：2012-08-21
申请人： Jin Il CHUNG , Jun Hyun CHUN , Jin Wook BURM , Dae Ho YUN
发明人： Jin Il CHUNG , Jun Hyun CHUN , Jin Wook BURM , Dae Ho YUN
IPC分类号： H03K5/22 , H04L27/02 , H04L27/06
CPC分类号： H03K5/249 , H04L25/4917 , H04L27/06
摘要： A rail-to-rail comparator including a first comparison unit connected to a first terminal and configured to compare differential input signals to differential reference voltages; a second comparison unit connected to a second terminal and configured to compare the differential input signals to the differential reference voltages; and an output unit configured to be driven in response to a clock signal and to generate a complementary output signal according to comparison results of the first and second comparison units.
摘要翻译：一种轨到轨比较器，包括连接到第一端子并被配置为将差分输入信号与差分参考电压进行比较的第一比较单元; 第二比较单元，连接到第二端子并且被配置为将差分输入信号与差分参考电压进行比较; 以及输出单元，被配置为响应于时钟信号被驱动，并且根据第一和第二比较单元的比较结果产生互补的输出信号。

3. 发明申请

US20130002322A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130002322A1
公开(公告)日：2013-01-03
申请号：US13448547
申请日：2012-04-17
申请人： Jin Il CHUNG
发明人： Jin Il CHUNG
IPC分类号： H03L7/08
CPC分类号： H03L7/0812
摘要： A semiconductor device includes a delay unit configured to delay an inputted clock to generate a delay clock, a selection unit configured to select and output one of the inputted clock and the delay clock, a delay locked loop configured to perform a delay locking operation using a signal delivered from the selection unit, and a selection control unit configured to control the selection unit in response to a comparison of one period of the inputted clock and a maximum delay value of the delay locked loop.
摘要翻译：半导体器件包括：延迟单元，被配置为延迟输入的时钟以产生延迟时钟;选择单元，被配置为选择并输出所输入的时钟和延迟时钟中的一个;延迟锁定环，被配置为使用从所述选择单元传送的信号;以及选择控制单元，被配置为响应于所述输入时钟的一个周期与所述延迟锁定环的最大延迟值的比较来控制所述选择单元。

4. 发明授权

US08040169B2 Delay locked loop circuit 有权
标题翻译：延时锁定回路电路
公开(公告)号：US08040169B2
公开(公告)日：2011-10-18
申请号：US12897208
申请日：2010-10-04
申请人： Jin-Il Chung , Hoon Choi
发明人： Jin-Il Chung , Hoon Choi
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0812
摘要： A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.
摘要翻译：延迟锁定环电路包括延迟锁定单元，其被配置为输出第一内部时钟和第二内部时钟，其上升沿与第一内部时钟同步，通过延迟补偿的外部时钟来补偿半导体的偏斜记忆装置; 占空比补偿单元，被配置为通过补偿半导体存储器件的外部时钟的占空比来产生补偿的外部时钟，并补偿第一和第二内部时钟的占空比; 以及时钟控制单元，被配置为在外部时钟的占空比补偿之后控制第二内部时钟的激活状态。

5. 发明申请

US20110018600A1 DELAY LOCKED LOOP CIRCUIT 有权
标题翻译：延迟锁定环路
公开(公告)号：US20110018600A1
公开(公告)日：2011-01-27
申请号：US12897208
申请日：2010-10-04
申请人： Jin-Il CHUNG , Hoon Choi
发明人： Jin-Il CHUNG , Hoon Choi
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0812
摘要： A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.
摘要翻译：延迟锁定环电路包括延迟锁定单元，其被配置为输出第一内部时钟和第二内部时钟，其上升沿与第一内部时钟同步，通过延迟补偿的外部时钟来补偿半导体的偏斜记忆装置; 占空比补偿单元，被配置为通过补偿半导体存储器件的外部时钟的占空比来产生补偿的外部时钟，并补偿第一和第二内部时钟的占空比; 以及时钟控制单元，被配置为在外部时钟的占空比补偿之后控制第二内部时钟的激活状态。

6. 发明授权

US07830187B2 Delay locked loop circuit 有权
标题翻译：延时锁定回路电路
公开(公告)号：US07830187B2
公开(公告)日：2010-11-09
申请号：US12327745
申请日：2008-12-03
申请人： Jin-Il Chung , Hoon Choi
发明人： Jin-Il Chung , Hoon Choi
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0812
摘要： A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.
摘要翻译：延迟锁定环电路包括延迟锁定单元，其被配置为输出第一内部时钟和第二内部时钟，其上升沿与第一内部时钟同步，通过延迟补偿的外部时钟来补偿半导体的偏斜记忆装置; 占空比补偿单元，被配置为通过补偿半导体存储器件的外部时钟的占空比来产生补偿的外部时钟，并补偿第一和第二内部时钟的占空比; 以及时钟控制单元，被配置为在外部时钟的占空比补偿之后控制第二内部时钟的激活状态。

7. 发明授权

US07773439B2 Test operation of multi-port memory device 有权
标题翻译：多端口存储设备的测试操作
公开(公告)号：US07773439B2
公开(公告)日：2010-08-10
申请号：US11647625
申请日：2006-12-28
申请人： Chang-Ho Do , Jin-Il Chung
发明人： Chang-Ho Do , Jin-Il Chung
IPC分类号： G11C7/00
CPC分类号： G11C29/14 , G11C7/1012 , G11C7/1075 , G11C29/1201 , G11C29/48 , G11C2207/107
摘要： A multi-port memory device includes a plurality ports, a plurality of banks, a plurality of global data buses, first and second I/O controllers, and a test input/output (I/O) controller. The ports perform a serial I/O data transmission. The banks perform a parallel I/O data transmission with the ports. The global data buses are employed for transmitting data between the ports and the banks. The first I/O controller controls a serial data transmission between the ports and external devices. The second I/O controller controls a parallel data transmission between the ports and the global buses. The test I/O controller generates test commands based on a test command/address (C/A) inputted from the external devices and transmits a test I/O data with the global data bus during a test operation mode.
摘要翻译：多端口存储器件包括多个端口，多个存储体，多个全局数据总线，第一和第二I / O控制器以及测试输入/输出（I / O）控制器。端口执行串行I / O数据传输。银行与端口执行并行I / O数据传输。全局数据总线用于在端口和银行之间传输数据。第一个I / O控制器控制端口和外部设备之间的串行数据传输。第二个I / O控制器控制端口和全局总线之间的并行数据传输。测试I / O控制器根据从外部设备输入的测试命令/地址（C / A）生成测试命令，并在测试操作模式期间与全局数据总线发送测试I / O数据。

8. 发明申请

US20100052745A1 DELAY LOCKED LOOP CIRCUIT 有权
标题翻译：延迟锁定环路
公开(公告)号：US20100052745A1
公开(公告)日：2010-03-04
申请号：US12327745
申请日：2008-12-03
申请人： Jin-Il CHUNG , Hoon CHOI
发明人： Jin-Il CHUNG , Hoon CHOI
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0812
摘要： A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.
摘要翻译：延迟锁定环电路包括延迟锁定单元，其被配置为输出第一内部时钟和第二内部时钟，其上升沿与第一内部时钟同步，通过延迟补偿的外部时钟来补偿半导体的偏斜记忆装置; 占空比补偿单元，被配置为通过补偿半导体存储器件的外部时钟的占空比来产生补偿的外部时钟，并补偿第一和第二内部时钟的占空比; 以及时钟控制单元，被配置为在外部时钟的占空比补偿之后控制第二内部时钟的激活状态。

9. 发明申请

US20090219775A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20090219775A1
公开(公告)日：2009-09-03
申请号：US12154870
申请日：2008-05-28
申请人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
发明人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
IPC分类号： G11C29/00 , G11C7/00 , G11C8/00
CPC分类号： G11C29/12 , G11C11/401
摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.
摘要翻译：半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元执行包括写入操作的多个内部操作来检测缺陷在晶圆级别。

10. 发明申请

US20110231717A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110231717A1
公开(公告)日：2011-09-22
申请号：US13149683
申请日：2011-05-31
申请人： Hwang HUR , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
发明人： Hwang HUR , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G11C29/12 , G11C11/401
摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.
摘要翻译：半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元来执行包括写入操作的多个内部操作来检测缺陷在晶圆级别。

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