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1. 发明授权

US06696328B2 CMOS gate electrode using selective growth and a fabrication method thereof 失效
标题翻译： CMOS栅电极及其制造方法
公开(公告)号：US06696328B2
公开(公告)日：2004-02-24
申请号：US10413387
申请日：2003-04-15
申请人： Hwa-sung Rhee , Geum-jong Bae , Sang-su Kim , Jung-il Lee , Young-ki Ha , Ki-chul Kim
发明人： Hwa-sung Rhee , Geum-jong Bae , Sang-su Kim , Jung-il Lee , Young-ki Ha , Ki-chul Kim
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , Y10S438/933
摘要： A CMOS gate electrode formed using a selective growth method and a fabrication method thereof, wherein, in the CMOS gate electrode, a first gate pattern of polysilicon germanium (poly-SiGe) is formed on a PMOS region of a semiconductor substrate, and a second gate pattern of polysilicon is selectively grown from an underlying layer. Although the first gate pattern on the PMOS region is formed of poly-SiGe, the characteristics of the second gate pattern on the NMOS region do not deteriorate, thereby increasing the overall characteristics of a CMOS transistor.
摘要翻译：一种使用选择性生长方法形成的CMOS栅电极及其制造方法，其中在CMOS栅电极中，在半导体衬底的PMOS区上形成多晶硅锗（poly-SiGe）的第一栅极图案，从下层选择性地生长多晶硅的栅极图案。尽管PMOS区上的第一栅极图案是由多晶硅形成的，但NMOS区域上的第二栅极图案的特性不会恶化，从而增加了CMOS晶体管的总体特性。

2. 发明授权

US06815320B2 Method for fabricating semiconductor device including gate spacer 有权
标题翻译：包括栅极间隔物的半导体器件的制造方法
公开(公告)号：US06815320B2
公开(公告)日：2004-11-09
申请号：US10444221
申请日：2003-05-23
申请人： Sang-su Kim , Geum-jong Bae , Ki-chul Kim , Jung-il Lee , Hwa-sung Rhee
发明人： Sang-su Kim , Geum-jong Bae , Ki-chul Kim , Jung-il Lee , Hwa-sung Rhee
IPC分类号： H01L213205
CPC分类号： H01L29/6653 , H01L21/823481 , H01L29/6656 , H01L29/6659
摘要： Provided is a method for fabricating a semiconductor device. According to the method, an insolating layer which defines an active region on a semiconductor substrate is formed and a gate is formed on the active region of the semiconductor substrate. A first spacer layer which covers the gate and is extended to cover the isolating layer is formed as a first insulating material. A second spacer layer is formed on the first spacer layer as a second insulating material. A second spacer which remains on the sidewalls of the gate by removing some portions of the second spacer layer is formed. A first spacer by a portion of the first spacer layer, which is protected by the second spacer by partially etching the exposed portions of the first spacer layer using the second spacer as a mask so as to reduce the thickness of the first spacer layer, and a protection layer, which protects the insulating layer by remaining the portion of the first spacer of which thickness is reduced, are formed. The second spacer is selectively removed and a gate spacer of the first spacer is formed by removing the remaining protection layer.
摘要翻译：提供一种制造半导体器件的方法。根据该方法，形成在半导体衬底上限定有源区的绝缘层，并且在半导体衬底的有源区上形成栅极。覆盖栅极并延伸以覆盖隔离层的第一间隔层形成为第一绝缘材料。第二间隔层作为第二绝缘材料形成在第一间隔层上。形成通过去除第二间隔层的一些部分而保留在栅极的侧壁上的第二间隔物。第一间隔物通过第一间隔层的一部分被第二间隔物保护，通过使用第二间隔物作为掩模部分蚀刻第一间隔层的暴露部分以减小第一间隔层的厚度，以及形成保护层，其通过保留厚度减小的第一间隔物的部分来保护绝缘层。选择性地去除第二间隔物，并且通过去除剩余的保护层来形成第一间隔物的栅极间隔物。

3. 发明授权

US06878580B2 Semiconductor device having gate with negative slope and method for manufacturing the same 有权
标题翻译：具有负斜率栅极的半导体器件及其制造方法
公开(公告)号：US06878580B2
公开(公告)日：2005-04-12
申请号：US10341563
申请日：2003-01-13
申请人： Geum-jong Bae , Nae-in Lee , Ki-chul Kim , Hwa-sung Rhee , Sang-su Kim , Jung-il Lee
发明人： Geum-jong Bae , Nae-in Lee , Ki-chul Kim , Hwa-sung Rhee , Sang-su Kim , Jung-il Lee
IPC分类号： H01L21/336 , H01L21/265 , H01L21/28 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/8234
CPC分类号： H01L21/26586 , H01L21/2807 , H01L21/28114 , H01L29/42376
摘要： A semiconductor device having a gate with a negative slope and a method of manufacturing the same. A poly-SiGe layer with a Ge density profile which decreases linearly from the bottom of the gate toward the top of the gate is formed and a poly-SiGe gate having a negative slope is formed by patterning the poly-SiGe layer. It is possible to form a gate whose bottom is shorter than its top defined by photolithography by taking advantage of the variation of etching characteristics with Ge density when patterning. Accordingly, the gate is compact enough for a short channel device and gate resistance can be reduced.
摘要翻译：一种具有负斜率栅极的半导体器件及其制造方法。形成具有从栅极底部向栅极顶部线性减小的Ge密度分布的多晶硅层，并且通过对多晶硅层进行构图来形成具有负斜率的多晶硅栅极。通过在图案化时利用Ge密度的蚀刻特性的变化，可以形成底部短于通过光刻限定的顶部的栅极。因此，门对于短通道器件足够紧凑，并且可以减小栅极电阻。

4. 发明申请

US20070117297A1 CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and method of forming same 有权
标题翻译：具有埋入硅锗层的CMOS集成电路器件和衬底及其形成方法
公开(公告)号：US20070117297A1
公开(公告)日：2007-05-24
申请号：US11656717
申请日：2007-01-23
申请人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
发明人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
IPC分类号： H01L21/8234
CPC分类号： H01L29/66916 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66742 , H01L29/78609 , H01L29/78612 , H01L29/78621 , H01L29/78687 , H01L29/802
摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2
摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结，并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小峰值电平朝向未应变硅活性层的表面。峰值Ge浓度水平大于x = 0.15，并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。更优选的是，Si 1-x Ge 2 x层中的Ge的浓度从0.2

5. 发明申请

US20050230676A1 Methods of forming CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and devices so formed 失效
标题翻译：形成CMOS集成电路器件和其中具有掩埋硅锗层的衬底的方法以及如此形成的器件
公开(公告)号：US20050230676A1
公开(公告)日：2005-10-20
申请号：US11141275
申请日：2005-06-01
申请人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
发明人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
IPC分类号： H01L21/336 , H01L21/337 , H01L21/762 , H01L27/12 , H01L29/10 , H01L29/786 , H01L29/80 , H01L29/06
CPC分类号： H01L29/66916 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66742 , H01L29/78609 , H01L29/78612 , H01L29/78621 , H01L29/78687 , H01L29/802
摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2
摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结，并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小峰值电平朝向未应变硅活性层的表面。峰值Ge浓度水平大于x = 0.15，并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。更优选的是，Si 1-x Ge 2 x层中的Ge的浓度从0.2

6. 发明授权

US06914301B2 CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same 有权
标题翻译：具有掩埋硅锗层的CMOS集成电路器件和衬底及其形成方法
公开(公告)号：US06914301B2
公开(公告)日：2005-07-05
申请号：US10685116
申请日：2003-10-14
申请人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
发明人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
IPC分类号： H01L21/336 , H01L21/337 , H01L21/762 , H01L27/12 , H01L29/10 , H01L29/786 , H01L29/80 , H01L27/01
CPC分类号： H01L29/66916 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66742 , H01L29/78609 , H01L29/78612 , H01L29/78621 , H01L29/78687 , H01L29/802
摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2
摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结，并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小峰值电平朝向未应变硅活性层的表面。峰值Ge浓度水平大于x = 0.15，并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。更优选的是，Si 1-x Ge 2 x层中的Ge的浓度从0.2

7. 发明授权

US07642140B2 CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and method of forming same 有权
标题翻译：具有埋入硅锗层的CMOS集成电路器件和衬底及其形成方法
公开(公告)号：US07642140B2
公开(公告)日：2010-01-05
申请号：US11656717
申请日：2007-01-23
申请人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
发明人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
IPC分类号： H01L21/84
CPC分类号： H01L29/66916 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66742 , H01L29/78609 , H01L29/78612 , H01L29/78621 , H01L29/78687 , H01L29/802
摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2
摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。绝缘栅电极也设置在未应变硅有源层的表面上。 Si1-xGex层也设置在电绝缘层和未应变硅有源层之间。 Si1-xGex层与未应变的硅有源层形成第一结，并且其中Ge的分级浓度在从峰值电平朝向未应变硅有源层的表面延伸的第一方向上单调减小。峰值Ge浓度水平大于x = 0.15，并且Si1-xGex层中的Ge浓度在第一结处从峰值水平变化到小于约x = 0.1的水平。 Ge在第一结处的浓度可能是突然的。更优选地，Si1-xGex层中的Ge的浓度从0.2

8. 发明授权

US07195987B2 Methods of forming CMOS integrated circuit devices and substrates having buried silicon germanium layers therein 有权
标题翻译：在其中形成CMOS集成电路器件和其中具有掩埋硅锗层的衬底的方法
公开(公告)号：US07195987B2
公开(公告)日：2007-03-27
申请号：US11141275
申请日：2005-05-31
申请人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
发明人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
IPC分类号： H01L21/76
CPC分类号： H01L29/66916 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66742 , H01L29/78609 , H01L29/78612 , H01L29/78621 , H01L29/78687 , H01L29/802
摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2
摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结，并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小峰值电平朝向未应变硅活性层的表面。峰值Ge浓度水平大于x = 0.15，并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。更优选的是，Si 1-x Ge 2 x层中的Ge的浓度从0.2

9. 发明授权

US06633066B1 CMOS integrated circuit devices and substrates having unstrained silicon active layers 失效
标题翻译： CMOS集成电路器件和具有非限制性硅有源层的衬底
公开(公告)号：US06633066B1
公开(公告)日：2003-10-14
申请号：US09711706
申请日：2000-11-13
申请人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
发明人： Geum-jong Bae , Tae-hee Choe , Sang-su Kim , Hwa-sung Rhee , Nae-in Lee , Kyung-wook Lee
IPC分类号： H01L310392
CPC分类号： H01L29/66916 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66742 , H01L29/78609 , H01L29/78612 , H01L29/78621 , H01L29/78687 , H01L29/802
摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1−xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1−xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peal Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1−xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1−xGex layer varies from the peak level where 0.2
摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。绝缘栅电极也设置在未应变硅有源层的表面上。还可以在电绝缘层和未应变硅活性层之间设置Si 1-x Ge x 层。 Si 1-x Ge x 层与未应变硅活性层形成第一结，并具有梯度浓度 Ge在从峰值电平向未应变硅有源层的表面延伸的第一方向上单调减小。 Peal Ge浓度水平大于x = 0.15，并且Si 1-x Ge x 层在峰值电平变化到在第一结处小于约x = 0.1的电平。 Ge在第一结处的浓度可能是突然的。更优选的是，Si >
层中的Ge的浓度， x <0.4到第一结处x = 0的水平。相对于表面，Si 1-x Ge x 层也具有退化的砷掺杂特性。 >

10. 发明申请

US20090085125A1 MOS transistor and CMOS transistor having strained channel epi layer and methods of fabricating the transistors 审中-公开
标题翻译：具有应变通道外延层的MOS晶体管和CMOS晶体管以及制造晶体管的方法
公开(公告)号：US20090085125A1
公开(公告)日：2009-04-02
申请号：US12285044
申请日：2008-09-29
申请人： Ki-Chul Kim , Hong-jae Shin , Moon-han Park , Hwa-sung Rhee , Jung-deog Lee
发明人： Ki-Chul Kim , Hong-jae Shin , Moon-han Park , Hwa-sung Rhee , Jung-deog Lee
IPC分类号： H01L27/092 , H01L29/94
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/66651 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： Provided are a metal oxide semiconductor (MOS) transistor and a complementary MOS (CMOS) transistor each having a strained channel epi layer, and methods of fabricating the transistors. The MOS transistor may include at least one active region defined by an isolation structure formed in a substrate. At least one channel trench may be formed in a part of the at least one active region. At least one strained channel epi layer may be in the at least one channel trench. At least one gate electrode may be aligned on the at least one strained channel epi layer. Sources/drains may be arranged in the at least one active region along both sides of the at least one strained channel epi layer.
摘要翻译：提供了具有应变通道外延层的金属氧化物半导体（MOS）晶体管和互补MOS（CMOS）晶体管，以及制造晶体管的方法。 MOS晶体管可以包括由形成在衬底中的隔离结构限定的至少一个有源区。至少一个通道沟槽可以形成在至少一个有源区域的一部分中。至少一个应变通道外延层可以在至少一个沟道沟槽中。至少一个栅极可以在至少一个应变通道外延层上对准。源/排水口可以布置在沿着至少一个应变通道外延层的两侧的至少一个有源区域中。

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