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1. 发明授权

US5761479A Upgradeable/downgradeable central processing unit chip computer systems 失效
标题翻译：可升级/降级中央处理单元芯片计算机系统
公开(公告)号：US5761479A
公开(公告)日：1998-06-02
申请号：US422081
申请日：1995-03-31
申请人： Hung-Ta Huang , Te-Chih Chuang , Yunn-Hung Liao , Yi-Hsien Lee , Lung Wei
发明人： Hung-Ta Huang , Te-Chih Chuang , Yunn-Hung Liao , Yi-Hsien Lee , Lung Wei
IPC分类号： G06F9/38 , G06F13/40 , G06F15/78 , G06F15/76
CPC分类号： G06F9/3879 , G06F13/4068 , G06F15/7864 , G06F9/3877
摘要： A single chip replacement upgradeable/downgradeable data processing system capable of operating with different types of central processing unit (CPU) chips. The system has a first socket for registration of a first CPU chip and a second socket for registration of a second CPU chip. Circuitry is provided for preventing possible signal contention between the first and second CPU chips and for synchronizing clocks for operating a CPU with the system clock. Circuitry is also provided for interfacing with a coprocessor associated with the different types of CPU chips as well as for adjusting the signals to and from the CPU chips to the signal width of the system.
摘要翻译：单芯片替换可升级/降级的数据处理系统，能够使用不同类型的中央处理器（CPU）芯片进行操作。该系统具有用于注册第一CPU芯片的第一插座和用于注册第二CPU芯片的第二插座。提供电路，用于防止第一和第二CPU芯片之间的可能的信号争用，并且用于同步用于与系统时钟一起操作CPU的时钟。还提供电路用于与与不同类型的CPU芯片相关联的协处理器的接口，以及用于将来自/或从CPU芯片的信号调整到系统的信号宽度。

2. 发明授权

US5551012A Single socket upgradeable computer motherboard with automatic detection and socket reconfiguration for inserted CPU chip 失效
标题翻译：单插座可升级计算机主板，具有自动检测和插座重新配置插入CPU芯片
公开(公告)号：US5551012A
公开(公告)日：1996-08-27
申请号：US208056
申请日：1994-03-08
申请人： Te-Chih Chuang , Yunn-Hung Liao , Lung Wei , Yi-Hsien Lee
发明人： Te-Chih Chuang , Yunn-Hung Liao , Lung Wei , Yi-Hsien Lee
IPC分类号： G06F13/40 , G06F15/78 , G06F15/76
CPC分类号： G06F9/3879 , G06F13/4063 , G06F13/4068 , G06F15/7832
摘要： An upgradeable/downgradeable computer system is made capable of being driven by more than one model of central processing units, including at least one socket means capable of being plugged with different model of central processing units, an identifying circuit capable of identifying the model of the central processing unit in the socket means and generating an identifying signal, a clock generator responsive to the identifying signal for generating a clock signal acceptable to the model of the central processing unit in the socket means, and a means responsive to the identifying signal for gating and inhibiting a plurality of input/output signals of the central processing unit in the socket means.
摘要翻译：可升级/可降级的计算机系统能够由多个中央处理单元型号驱动，包括至少一个能够用不同型号的中央处理单元插入的插座装置，能识别的模型的识别电路插座装置中的中央处理单元，并产生识别信号;响应于识别信号的时钟发生器，用于产生插座装置中的中央处理单元的模型可接受的时钟信号，以及响应识别信号进行选通的装置以及禁止插座装置中的中央处理单元的多个输入/输出信号。

3. 发明授权

US06502159B1 Method and apparatus for increasing data throughput in a computer system 有权
标题翻译：用于增加计算机系统中的数据吞吐量的方法和装置
公开(公告)号：US06502159B1
公开(公告)日：2002-12-31
申请号：US09608578
申请日：2000-06-30
申请人： Te-Chih Chuang , Hsueh-Wei Huang , Hsi-Yuan Hsu
发明人： Te-Chih Chuang , Hsueh-Wei Huang , Hsi-Yuan Hsu
IPC分类号： G06F1300
CPC分类号： H04N21/42692 , H04N21/4143 , H04N21/42646
摘要： Techniques for improving overall data throughput in a computer system, especially during the playing of movies from CD-ROMs provides for a direct flow of data between the CD-ROM and the MPEG card, greatly reducing system memory usage and bus utilization. Control circuitry is responsive to signals from the CPU, which signals specify whether data from the CD-ROM can be sent directly to the MPEG decoder circuit or needs to be sent over the buses to the system memory. Accordingly, different transmission paths are used, depending on the attribute and destination of the data in order to reduce unnecessary data flow in the system and unnecessary consumption of system resources.
摘要翻译：用于改善计算机系统中的整体数据吞吐量的技术，特别是在从CD-ROM播放电影期间提供CD-ROM和MPEG卡之间的数据的直接流动，大大降低了系统存储器使用和总线利用率。控制电路响应于来自CPU的信号，该信号指定来自CD-ROM的数据是否可以直接发送到MPEG解码器电路，或者需要通过总线发送到系统存储器。因此，根据数据的属性和目的地，使用不同的传输路径，以减少系统中的不必要的数据流，并且不必要地消耗系统资源。

4. 发明授权

US5632026A System and method for managing the routine execution in a computer system 失效
标题翻译：用于管理计算机系统中的例程执行的系统和方法
公开(公告)号：US5632026A
公开(公告)日：1997-05-20
申请号：US396380
申请日：1995-02-28
申请人： Te-Chih Chuang
发明人： Te-Chih Chuang
IPC分类号： G04C3/00 , G04C21/14 , G04G13/00 , G06F12/06 , G06F12/08 , G10L13/00 , G06F12/16
CPC分类号： G06F12/0888 , G06F12/0804 , G06F12/0891 , G06F12/0638
摘要： A computer program management system having a first memory device containing firmware, a shadow processing device for copying the firmware from the first memory device to a shadow region of a system memory device, a cache RAM, and a flush device. Firmware is copied from the shadow region of the system memory device to the cache RAM for execution by the CPU. If an attempt is made to write to the shadow region of the system memory device, the flush device causes the CPU to flush the contents of the cache RAM.Alternatively, the system may have a first memory device containing firmware, a shadow processing device for copying the firmware from the first memory device to a shadow region of a system memory device, a cache RAM, and a disabling device. In this embodiment of an attempt is made to write to the shadow region of the system memory device, the disabling device causes the CPU to prevent the data from being written to the cache RAM.
摘要翻译：一种具有包含固件的第一存储装置的计算机程序管理系统，用于将固件从第一存储装置复制到系统存储装置的阴影区域的影子处理装置，高速缓冲存储器RAM和冲洗装置。固件从系统存储设备的阴影区域复制到高速缓存RAM，以供CPU执行。如果尝试写入系统存储器件的阴影区域，则刷新装置使CPU刷新高速缓存RAM的内容。或者，系统可以具有包含固件的第一存储器设备，用于将固件从第一存储器设备复制到系统存储器设备的阴影区域的影子处理设备，高速缓存RAM和禁用设备。在该实施例中，尝试写入系统存储器件的阴影区域时，禁用装置使CPU防止将数据写入高速缓存RAM。

5. 发明授权

US5546563A Single chip replacement upgradeable computer motherboard with enablement of inserted upgrade CPU chip 失效
标题翻译：单芯片更换可升级计算机主板，支持插入升级CPU芯片
公开(公告)号：US5546563A
公开(公告)日：1996-08-13
申请号：US177648
申请日：1994-01-04
申请人： Te-Chih Chuang
发明人： Te-Chih Chuang
IPC分类号： G06F1/18 , G06F1/04 , G06F3/00 , G06F13/14 , G06F13/40 , G06F15/78 , G06F15/76
CPC分类号： G06F9/3879 , G06F13/4063 , G06F13/4068 , G06F15/7832
摘要： A computer system is made capable of accepting more than one type of central processor including a plurality of sockets for receiving more than one type of identification signal, a clock generator responsive to said identifying signal for generating clock signals for the identified type of processor, and means responsive to said identifying signal for disabling and enabling signal paths from the socket.
摘要翻译：计算机系统能够接受多于一种类型的中央处理器，其包括用于接收多于一种类型的识别信号的多个插座;响应于所述识别信号的时钟发生器，用于为所识别的类型的处理器生成时钟信号;以及响应于所述识别信号的装置，用于禁用并启用来自插座的信号路径。

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