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    • 3. 发明授权
    • Display device controller and method
    • 显示设备控制器和方法
    • US5229758A
    • 1993-07-20
    • US755305
    • 1991-09-05
    • Hsi-Yuan Hsu
    • Hsi-Yuan Hsu
    • G09G5/36G09G5/39
    • G09G5/363G09G5/39G09G2360/121
    • A display device controller with improved read performance comprises video memory, a video display control unit, video processing logic, a write buffer and a read buffer. The write buffer and read buffer are coupled between a CPU and the video memory for transferring information between the CPU and video memory. In the preferred embodiment, the read buffer further comprises an address latch, a control circuit, a first buffer, a second buffer, a multiplexer and a counter. The control circuit stores addresses in the address latch, reads video memory, and stores the data in the first and second buffers. The control circuit determines the output to the CPU by controlling the multiplexer. The control circuit is also responsive to the counter and the read buffer is partially disabled if the miss rate is a high to reduce the negative consequences of the additional information read by the control circuit.
    • 具有改进的读取性能的显示设备控制器包括视频存储器,视频显示控制单元,视频处理逻辑,写入缓冲器和读取缓冲器。 写缓冲器和读缓冲器耦合在CPU和视频存储器之间,用于在CPU和视频存储器之间传送信息。 在优选实施例中,读缓冲器还包括地址锁存器,控制电路,第一缓冲器,第二缓冲器,多路复用器和计数器。 控制电路存储地址锁存器中的地址,读取视频存储器,并将数据存储在第一和第二缓冲器中。 控制电路通过控制多路复用器来确定CPU的输出。 控制电路还响应于计数器,并且如果错误率是高的,则读取缓冲器被部分地禁用,以减少由控制电路读取的附加信息的负面后果。