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    • 1. 发明申请
    • Liquid crystal display device
    • 液晶显示装置
    • US20070115420A1
    • 2007-05-24
    • US11284941
    • 2005-11-21
    • Hung-Jen ChuCheng-Chung HuWen-Hsiung LiuHsian-Ching Chiu
    • Hung-Jen ChuCheng-Chung HuWen-Hsiung LiuHsian-Ching Chiu
    • G02F1/1339
    • G02F1/13394G02F2001/13396
    • An LCD device comprises a TFT array substrate, a color filter substrate and a LC layer sandwiched therebetween. On the TFT array and color filter substrates, a plurality of first and second protrusions and spacers are provided, respectively. When the TFT array and color filter substrates are assembled together, each of the plurality of first and second protrusions and a corresponding one of the plurality of first and second spacers are aligned to each other and have a gap provided therebetween, in which the LC layer is positioned where LC material is filled. The plurality of first protrusions and a corresponding one of the plurality of first spacers are brought into contact with each other and the plurality of second protrusions and a corresponding one of the plurality of second spacers are also brought into contact with each other while a space margin is provided therebetween.
    • LCD装置包括TFT阵列基板,滤色器基板和夹在其间的LC层。 在TFT阵列和滤色器基板上分别设置多个第一和第二突起和间隔物。 当TFT阵列和滤色器基板组装在一起时,多个第一和第二突起中的每一个和多个第一和第二间隔物中的相应一个彼此对准并且在它们之间具有间隙,其中LC层 位于LC材料填充的位置。 多个第一突起和多个第一间隔件中的相应一个彼此接触,并且多个第二突起和多个第二间隔件中的相应一个也彼此接触,同时空隙 设置在其间。
    • 2. 发明申请
    • Thin film transistor array
    • 薄膜晶体管阵列
    • US20070296882A1
    • 2007-12-27
    • US11473946
    • 2006-06-23
    • Jau-Ching HuangChien-Chih JenHuei-Chung YuMeng-Feng HungWen-Hsiung LiuHung-Jen Chu
    • Jau-Ching HuangChien-Chih JenHuei-Chung YuMeng-Feng HungWen-Hsiung LiuHung-Jen Chu
    • G02F1/136
    • G02F1/136286G02F1/136213G02F2001/13606
    • A thin film transistor array comprising a substrate, thin film transistors, pixel electrodes, common lines, and auxiliary electrodes disposed on the substrate is provided. The substrate has a plurality of pixel regions, and each of the thin film transistors, pixel electrodes, and auxiliary electrodes are disposed in each pixel region. In each pixel region, the pixel electrode is covered over the common line and is electrically connected to the thin film transistor. The auxiliary electrode is located between the pixel electrode and the common line, and the area of the overlapping region between the auxiliary electrode and the common line is L×H, while the sum of the side lengths of the overlapping region is more than 2L×2H, wherein L and H are both positive real numbers. The individual feed-through voltages in each pixel regions in the thin film transistor array are the same.
    • 提供一种薄膜晶体管阵列,其包括设置在基板上的基板,薄膜晶体管,像素电极,公共线以及辅助电极。 基板具有多个像素区域,并且薄膜晶体管,像素电极和辅助电极中的每一个设置在每个像素区域中。 在每个像素区域中,像素电极被覆盖在公共线上并与薄膜晶体管电连接。 辅助电极位于像素电极和公共线之间,辅助电极和公共线之间的重叠区域的面积为LxH,而重叠区域的边长之和大于2Lx2H,其中L 和H都是正实数。 薄膜晶体管阵列中每个像素区域中的各个馈通电压是相同的。
    • 3. 发明申请
    • ACTIVE DEVICE ARRAY SUBSTRATE
    • 主动设备阵列基板
    • US20090014726A1
    • 2009-01-15
    • US12144655
    • 2008-06-24
    • Wen-Hsiung LiuChien-Kuo He
    • Wen-Hsiung LiuChien-Kuo He
    • H01L33/00
    • H01L27/0248H01L27/12H01L27/1214
    • An active device array substrate including a substrate, a pixel array, pads, first switching devices, and second switching devices is provided. The pixel array is disposed on a display region of the substrate. The pads, the first and the second switching devices are disposed on a peripheral circuit region of the substrate. The pads and the pixel array are electrically connected. The first and the second switching devices are at the outside of the pads. Each first switching device is electrically connected to one of the pads and has a source, a drain, and a gate electrically connected to the source and the pad. Each second switching device is electrically connected to two adjacent first switching devices and has a gate, a source, and a drain. The source and the drain are electrically connected to the drain and the source of the adjacent first switching device, respectively.
    • 提供了包括衬底,像素阵列,焊盘,第一开关器件和第二开关器件的有源器件阵列衬底。 像素阵列设置在基板的显示区域上。 焊盘,第一和第二开关器件设置在衬底的外围电路区域上。 焊盘和像素阵列电连接。 第一和第二开关器件位于焊盘的外部。 每个第一开关器件电连接到焊盘中的一个,并且具有电源连接到源极和焊盘的源极,漏极和栅极。 每个第二开关装置电连接到两个相邻的第一开关装置,并具有栅极,源极和漏极。 源极和漏极分别电连接到相邻的第一开关器件的漏极和源极。
    • 4. 发明申请
    • ACTIVE DEVICES ARRAY SUBSTRATE AND REPAIRING METHOD THEREOF
    • 主动装置阵列基板及其修复方法
    • US20080006858A1
    • 2008-01-10
    • US11309007
    • 2006-06-08
    • Wen-Hsiung Liu
    • Wen-Hsiung Liu
    • H01L31/062H01L31/113
    • G02F1/1345G02F1/136204G02F2001/133388
    • An active device array substrate including a substrate, a plurality of active devices, a plurality of the first lead lines, a plurality of the second lead lines and a first floating light-shielding layer is provided. The substrate has a display region and a peripheral circuit region and the active devices are arranged within the peripheral circuit region on the substrate to form an array. Besides, the first lead lines and the second lead lines are disposed within the peripheral circuit region on the substrate. The first floating light-shielding layer is disposed between the first lead lines and covers the part of the first lead lines. Furthermore, the floating light-shielding layer is not connected with any voltage sources completely. Therefore, the active devices array substrate can prevent the light leakage from been resulted between the first lead lines and the power consumption of the active devices array substrate is reduced.
    • 提供一种有源器件阵列基板,包括基板,多个有源器件,多个第一引线,多个第二引线和第一浮动遮光层。 衬底具有显示区域和外围电路区域,并且有源器件布置在衬底上的外围电路区域内以形成阵列。 此外,第一引线和第二引线设置在基板上的外围电路区域内。 第一浮动遮光层设置在第一引线之间并覆盖第一引线的一部分。 此外,浮动遮光层不与任何电压源完全连接。 因此,有源器件阵列衬底可以防止在第一引线之间产生光泄漏,并且有源器件阵列衬底的功耗降低。
    • 5. 发明申请
    • Pixel structure and liquid crystal display panel thereof
    • 像素结构及其液晶显示面板
    • US20070229722A1
    • 2007-10-04
    • US11397659
    • 2006-04-03
    • Wen-Hsiung Liu
    • Wen-Hsiung Liu
    • G02F1/136
    • G02F1/1368
    • A pixel structure comprising a substrate, a first metal layer, a first dielectric layer, a semiconductor layer, a second metal layer and a pixel electrode is provided. The first metal layer, disposed on the substrate, includes a gate and a scan line. The first dielectric layer covers the first metal layer. The semiconductor layer is disposed on the first dielectric layer above the gate. The second metal layer includes a source, a drain and a data line connected with the source. The pixel electrode is electrically connected with the drain. Wherein, the drain has a main body and an extension portion projecting out of the scan line. The main body has a first length (L1). The interface of the extension portion and the scan line is a second length (L2). The L1/L2 is predetermined such that the Cgd of the pixel structure is fixed.
    • 提供了包括基板,第一金属层,第一介电层,半导体层,第二金属层和像素电极的像素结构。 设置在基板上的第一金属层包括栅极和扫描线。 第一介电层覆盖第一金属层。 半导体层设置在栅极上方的第一电介质层上。 第二金属层包括源极,漏极和与源极连接的数据线。 像素电极与漏极电连接。 其中,排水口具有从扫描线突出的主体和延伸部分。 主体具有第一长度(L 1)。 延伸部分和扫描线的界面是第二长度(L 2)。 L 1 / L 2是预定的,使得像素结构的Cgd是固定的。
    • 6. 发明申请
    • THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY AND REPAIRING METHOD THEREOF
    • 薄膜晶体管,薄膜晶体管阵列及其修复方法
    • US20070187686A1
    • 2007-08-16
    • US11307540
    • 2006-02-13
    • Wen-Hsiung Liu
    • Wen-Hsiung Liu
    • H01L29/04
    • H01L27/124G02F2001/13606G02F2001/13625G02F2001/136268H01L29/66757
    • A thin film transistor (TFT) including a gate, a semiconductor layer, a source and a drain is provided. The gate has a control part, a connection part and a capacitance compensation part. The connection part is disposed between the control part and the capacitance compensation part for joining the two parts together. The semiconductor layer is disposed over the gate, the source and the drain are disposed on the semiconductor layer. An end of the drain overlaps the control part of the gate with a first region for composing a first parasitic capacitance; while another end of the drain overlaps the capacitance compensation part of the gate with a second region for composing a second parasitic capacitance. In a TFT array with the TFT, the sum of the first parasitic capacitance and the second parasitic capacitance is a constant.
    • 提供了包括栅极,半导体层,源极和漏极的薄膜晶体管(TFT)。 门具有控制部分,连接部分和电容补偿部分。 连接部设置在控制部和电容补偿部之间,用于将两部分接合在一起。 半导体层设置在栅极上方,源极和漏极设置在半导体层上。 漏极的一端与门的控制部分重叠用于构成第一寄生电容的第一区域; 而漏极的另一端与栅极的电容补偿部分重叠用于构成第二寄生电容的第二区域。 在具有TFT的TFT阵列中,第一寄生电容和第二寄生电容之和为常数。
    • 10. 发明申请
    • DISPLAY PANEL AND DRIVING METHOD THEREOF
    • 显示面板及其驱动方法
    • US20090160850A1
    • 2009-06-25
    • US12341974
    • 2008-12-22
    • Yuan-Hsin TsouWen-Hsiung Liu
    • Yuan-Hsin TsouWen-Hsiung Liu
    • G06F3/038G09G3/20G09G3/36
    • G09G3/3648G09G3/3607G09G2300/0452G09G2300/0804
    • A display panel including a number of data lines and scan lines, a number of first, second, and third switches, and a number of first, second, and third pixels is provided. Each first pixel located at an odd position at a first side of each data line is electrically connected to the corresponding data line through one first switch. Each second pixel located at an even position at the first side of each data line is electrically connected to the corresponding data line through the first, second, and third switches sequentially connected in series. Each third pixel located at a second side of each data line is electrically connected to the corresponding data line through the second and third switches sequentially connected in series. The first, second and third pixels are driven by corresponding scan lines and data lines. A driving method of the display panel is also provided.
    • 提供了包括多个数据线和扫描线,多个第一,第二和第三开关以及多个第一,第二和第三像素的显示面板。 位于每个数据线的第一侧的奇数位置的每个第一像素通过一个第一开关电连接到对应的数据线。 位于每条数据线的第一侧的偶数位置处的每个第二像素通过串联顺序连接的第一,第二和第三开关电连接到对应的数据线。 位于每个数据线的第二侧的每个第三像素通过串联顺序连接的第二和第三开关电连接到相应的数据线。 第一,第二和第三像素由相应的扫描线和数据线驱动。 还提供了显示面板的驱动方法。