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1. 发明申请

US20050191947A1 Retaining ring with shaped surface 有权
标题翻译：带环形表面的保持环
公开(公告)号：US20050191947A1
公开(公告)日：2005-09-01
申请号：US10988211
申请日：2004-11-12
申请人： Hung Chen , Steven Zuniga , Charles Garretson , Douglas McAllister , Jian Lin , Stacy Meyer , Sidney Huey , Jeonghoon Oh , Trung Doan , Jeffrey Schmidt , Martin Wohlert , Kerry Hughes , James Wang , Danny Cam Lu , Romain Beau De Lamenie , Venkata Balagani , Aden Allen , Michael Fong
发明人： Hung Chen , Steven Zuniga , Charles Garretson , Douglas McAllister , Jian Lin , Stacy Meyer , Sidney Huey , Jeonghoon Oh , Trung Doan , Jeffrey Schmidt , Martin Wohlert , Kerry Hughes , James Wang , Danny Cam Lu , Romain Beau De Lamenie , Venkata Balagani , Aden Allen , Michael Fong
IPC分类号： B24B37/32 , B24B1/00
CPC分类号： B24B37/32 , Y10T29/49815
摘要： A retaining ring can be shaped by machining or lapping the bottom surface of the ring to form a shaped profile in the bottom surface. The bottom surface of the retaining ring can include flat, sloped and curved portions. The lapping can be performed using a machine that dedicated for use in lapping the bottom surface of retaining rings. During the lapping the ring can be permitted to rotate freely about an axis of the ring. The bottom surface of the retaining ring can have curved or flat portions.
摘要翻译：保持环可以通过机械加工或研磨环的底部表面而在底面形成成形轮廓。保持环的底面可以包括平坦的，倾斜的和弯曲的部分。可以使用专用于研磨保持环底面的机器进行研磨。在研磨期间，可以允许环围绕环的轴线自由旋转。保持环的底面可以具有弯曲或平坦的部分。

2. 发明申请

US20070143980A1 Attaching components of a carrier head 失效
标题翻译：安装承载头的部件
公开(公告)号：US20070143980A1
公开(公告)日：2007-06-28
申请号：US11233154
申请日：2005-09-21
申请人： Trung Doan , Jeffrey Schmidt , Douglas McAllister , Stacy Meyer
发明人： Trung Doan , Jeffrey Schmidt , Douglas McAllister , Stacy Meyer
IPC分类号： B23Q17/00 , B23P19/00
CPC分类号： B24B37/32 , Y10T29/49764 , Y10T29/49766 , Y10T29/49769 , Y10T29/49771 , Y10T29/49778 , Y10T29/4978 , Y10T29/49947 , Y10T29/53039 , Y10T29/5343
摘要： Techniques for attaching a retaining ring to a carrier head so that the bottom surface of the retaining ring is orthogonal to a central rotational axis of the carrier head are described.
摘要翻译：描述了用于将保持环附接到承载头使得保持环的底表面与载体头的中心旋转轴线正交的技术。

3. 发明申请

US20080032480A1 SEMICONDUCTOR STRUCTURES INCLUDING VERTICAL DIODE STRUCTURES AND METHODS OF MAKING THE SAME 失效
标题翻译：包括垂直二极管结构的半导体结构及其制造方法
公开(公告)号：US20080032480A1
公开(公告)日：2008-02-07
申请号：US11869012
申请日：2007-10-09
申请人： Fernando Gonzalez , Tyler Lowrey , Trung Doan , Raymond Turi , Graham Wolstenholme
发明人： Fernando Gonzalez , Tyler Lowrey , Trung Doan , Raymond Turi , Graham Wolstenholme
IPC分类号： H01L21/20 , H01L29/00
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/2022 , H01L27/0814 , H01L27/101 , H01L27/1021 , H01L27/24 , H01L29/6609 , H01L29/66136 , H01L29/861 , H01L45/04 , H01L45/145 , Y10S257/903 , Y10S257/91 , Y10S438/979
摘要： Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.
摘要翻译：提供了制造垂直二极管结构的半导体结构和方法。垂直二极管结构可以具有延伸穿过绝缘层并接触硅晶片上的有源区的二极管开口。硅化钛层可以形成在二极管开口的内表面上并与活性区接触。二极管开口最初可以填充非晶硅插塞，其在沉积期间被掺杂并随后重结晶以形成大晶粒多晶硅。硅插头具有可以重掺杂第一类型掺杂剂的顶部部分和可以轻掺杂第二类型掺杂剂的底部部分。顶部可以由底部限定，以便不与硅化钛层接触。在垂直二极管结构的一个实施例中，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

4. 发明申请

US20080019167A1 CONTROLLABLE OVONIC PHASE-CHANGE SEMICONDUCTOR MEMORY DEVICE AND METHODS OF PROGRAMMING THE SAME 有权
标题翻译：可控的相位变化半导体存储器件及其编程方法
公开(公告)号：US20080019167A1
公开(公告)日：2008-01-24
申请号：US11833034
申请日：2007-08-02
申请人： Trung Doan , D. Durcan , Brent Gilgen
发明人： Trung Doan , D. Durcan , Brent Gilgen
IPC分类号： G11C11/00 , H01L29/04
CPC分类号： H01L45/06 , G11C2213/52 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of programming the same are disclosed. Such memory devices include a lower electrode including non-parallel sidewalls. An insulative material overlies the lower electrode such that an upper surface of the lower electrode is exposed. In one embodiment, the insulative material and lower electrode may have a co-planar upper surface. In another embodiment, an upper surface of the lower electrode is within a recess in the insulative material. A chalcogenide material and an upper electrode are formed over the upper surface of the lower electrode. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.
摘要翻译：公开了一种在硫族化物存储器的电极之间具有减小的接触面积的超声相变半导体存储器件及其编程方法。这种存储器件包括包括非平行侧壁的下电极。绝缘材料覆盖下电极，使得下电极的上表面露出。在一个实施例中，绝缘材料和下电极可以具有共面上表面。在另一个实施例中，下电极的上表面在绝缘材料的凹槽内。硫族化物材料和上电极形成在下电极的上表面上。这允许使存储器单元变得更小并且允许最小化存储器单元的总体功率需求。

5. 发明申请

US20070281487A1 METHOD FOR AN INTEGRATED CIRCUIT CONTACT 失效
标题翻译：集成电路联系方法
公开(公告)号：US20070281487A1
公开(公告)日：2007-12-06
申请号：US11841906
申请日：2007-08-20
申请人： Charles Dennison , Trung Doan
发明人： Charles Dennison , Trung Doan
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.
摘要翻译：在集成电路和器件的制造中提供用于形成垂直触点的工艺。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间可以重复上述过程。

6. 发明申请

US20070231963A1 METHOD FOR HANDLING A SEMICONDUCTOR WAFER ASSEMBLY 有权
标题翻译：用于处理半导体波长组件的方法
公开(公告)号：US20070231963A1
公开(公告)日：2007-10-04
申请号：US11758475
申请日：2007-06-05
申请人： Trung Doan , Chen-Fu Chu
发明人： Trung Doan , Chen-Fu Chu
IPC分类号： H01L21/00
CPC分类号： H01L33/0079
摘要： Systems and methods for fabricating a light emitting diode include forming a multilayer epitaxial structure above a carrier substrate; depositing at least one metal layer above the multilayer epitaxial structure; removing the carrier substrate.
摘要翻译：用于制造发光二极管的系统和方法包括在载体衬底上形成多层外延结构; 在所述多层外延结构上沉积至少一个金属层; 去除载体衬底。

7. 发明申请

US20060223425A1 Semiconductor processing methods of removing conductive material 有权
公开(公告)号：US20060223425A1
公开(公告)日：2006-10-05
申请号：US11449201
申请日：2006-06-05
申请人： Trung Doan , Scott Meikle
发明人： Trung Doan , Scott Meikle
IPC分类号： B24B7/30
CPC分类号： B24B37/11 , B23H5/08 , B24B37/042 , B24B37/046 , B24B37/20 , C25F3/30 , H01L21/3212 , H01L21/32125
摘要： The invention includes a semiconductive processing method of electrochemical-mechanical removing at least some of a conductive material from over a surface of a semiconductor substrate. A cathode is provided at a first location of the wafer, and an anode is provided at a second location of the wafer. The conductive material is polished with the polishing pad polishing surface. The polishing occurs at a region of the conductive material and not at another region. The region where the polishing occurs is defined as a polishing operation location. The polishing operation location is displaced across the surface of the substrate from said second location of the substrate toward said first location of the substrate. The polishing operation location is not displaced from said first location toward said second location when the polishing operation location is between the first and second locations. The invention also includes a semiconductor processing method of removing at least some of a conductive material from over a surface of a semiconductive material wafer. A polishing pad is displaced across an upper surface of the wafer from a central region of the wafer toward a periphery of the wafer, and is not displaced from the periphery to the central region.

8. 发明申请

US20060183349A1 Semiconductor component having thinned die with polymer layers 有权
标题翻译：半导体元件具有具有聚合物层的薄模
公开(公告)号：US20060183349A1
公开(公告)日：2006-08-17
申请号：US11390321
申请日：2006-03-27
申请人： Warren Farnworth , Alan Wood , Trung Doan
发明人： Warren Farnworth , Alan Wood , Trung Doan
IPC分类号： H01L21/31 , H01L23/28 , H01L23/34
CPC分类号： H01L23/48 , B33Y70/00 , B33Y80/00 , H01L21/304 , H01L21/3043 , H01L21/56 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L21/76802 , H01L21/76898 , H01L21/78 , H01L23/24 , H01L23/3114 , H01L23/36 , H01L23/3672 , H01L23/481 , H01L23/49531 , H01L23/49575 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/27 , H01L24/94 , H01L24/96 , H01L25/105 , H01L25/50 , H01L29/0657 , H01L2221/68327 , H01L2221/68331 , H01L2221/68372 , H01L2224/0401 , H01L2224/05599 , H01L2224/11849 , H01L2224/11901 , H01L2224/12105 , H01L2224/13009 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/16 , H01L2224/16235 , H01L2224/274 , H01L2224/73104 , H01L2224/73253 , H01L2224/94 , H01L2225/06541 , H01L2225/1035 , H01L2225/1058 , H01L2225/107 , H01L2225/1094 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01041 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/19041 , H01L2924/19042 , H01L2924/3512 , H01L2924/00 , H01L2224/29099 , H01L2224/27
摘要： A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.
摘要翻译：半导体部件包括在六个表面上具有保护性聚合物层的变薄的半导体管芯。该组件还包括嵌入在电路侧聚合物层中的裸片上的接触凸块，并且密集区域阵列中接触凸块上的端子接触。一种用于制造该部件的方法包括以下步骤：提供包含多个骰子的基底，在基底上邻近骰子的周边边缘形成沟槽，以及将聚合物材料沉积到沟槽中。此外，该方法包括以下步骤：平坦化衬底的背面以接触聚合物填充的沟槽，并切割穿过聚合物沟槽以从衬底中分离组分。在分离步骤之前，组分可以在它们保留在基材上时被测试和燃烧。

9. 发明申请

US20060154392A1 Method of making a vertical light emitting diode 有权
标题翻译：制造垂直发光二极管的方法
公开(公告)号：US20060154392A1
公开(公告)日：2006-07-13
申请号：US11032881
申请日：2005-01-11
申请人： Chuong Tran , Trung Doan
发明人： Chuong Tran , Trung Doan
IPC分类号： H01L21/00
CPC分类号： H01L33/22 , H01L33/42
摘要： Methods are disclosed for forming a vertical semiconductor light emitting diode (VLED) device having an active layer between an n-doped layer and a p-doped layer; and securing a plurality of balls on a surface of the n-doped layer of the VLED device.
摘要翻译：公开了用于形成在n掺杂层和p掺杂层之间具有有源层的垂直半导体发光二极管（VLED）器件的方法; 以及将多个球固定在VLED装置的n掺杂层的表面上。

10. 发明申请

US20060115957A1 Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature workpieces 有权
标题翻译：微型工件加工设备及控制材料沉积在微型工件上的方法
公开(公告)号：US20060115957A1
公开(公告)日：2006-06-01
申请号：US11327794
申请日：2006-01-06
申请人： Cem Basceri , Trung Doan , Ronald Weimer , Kevin Beaman , Lyle Breiner , Lingyi Zheng , Er-Xuan Ping , Demetrius Sarigiannis , David Kubista
发明人： Cem Basceri , Trung Doan , Ronald Weimer , Kevin Beaman , Lyle Breiner , Lingyi Zheng , Er-Xuan Ping , Demetrius Sarigiannis , David Kubista
IPC分类号： H01L21/76 , H01L21/20 , H01L21/302
CPC分类号： C23C16/45527 , C23C16/34 , C23C16/45546
摘要： The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.
摘要翻译：本公开提供了用于在批次的微特征工件上沉积材料中有用的方法和装置。一个实施方案提供了一种方法，其中一定量的第一前体气体以第一封壳压力被引入外壳。当以第一流速引入吹扫气体时，外壳内的压力降低到第二封闭压力。第二外壳压力可接近或等于处理系统在第一流量下的稳态基础压力。在降低压力之后，吹扫气体流量可以增加到第二流量，并且外壳压力可以增加到第三外壳压力。此后，第二前体气体的流动可以在第四封闭压力下以外壳内的压力引入; 第三外壳压力理想地在第四外壳压力的约10％内。

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