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1. 发明授权

US07485521B2 Self-aligned dual stressed layers for NFET and PFET 有权
标题翻译：用于NFET和PFET的自对准双应力层
公开(公告)号：US07485521B2
公开(公告)日：2009-02-03
申请号：US11160676
申请日：2005-07-05
申请人： Huilong Zhu , Brian L. Tessier , Huicai Zhong
发明人： Huilong Zhu , Brian L. Tessier , Huicai Zhong
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823828 , H01L29/7843 , Y10S438/938
摘要： Methods are disclosed for forming self-aligned dual stressed layers for enhancing the performance of NFETs and PFETs. In one embodiment, a sacrificial layer is used to remove a previously deposited stressed layer. A mask position used to pattern the sacrificial layer is adjusted such that removal of the latter deposited stressed layer, using the sacrificial layer, leaves the dual stress layers in an aligned form. The methods result in dual stressed layers that do not overlap or underlap, thus avoiding processing problems created by those issues. A semiconductor device including the aligned dual stressed layers is also disclosed.
摘要翻译：公开了用于形成用于增强NFET和PFET的性能的自对准双应力层的方法。在一个实施例中，牺牲层用于去除先前沉积的应力层。调整用于图案化牺牲层的掩模位置，使得使用牺牲层去除后者沉积的应力层以对准的形式离开双应力层。这种方法导致双重应力层不重叠或不重叠，从而避免了由这些问题产生的处理问题。还公开了包括对准的双重应力层的半导体器件。

2. 发明授权

US07244644B2 Undercut and residual spacer prevention for dual stressed layers 有权
标题翻译：双应力层的底切和剩余间隔物预防
公开(公告)号：US07244644B2
公开(公告)日：2007-07-17
申请号：US11161067
申请日：2005-07-21
申请人： Huilong Zhu , Brian L. Tessier , Huicai Zhong , Ying Li
发明人： Huilong Zhu , Brian L. Tessier , Huicai Zhong , Ying Li
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer over the NFET and the PFET, forming a sacrificial layer over the first stressed silicon nitride layer such that the sacrificial layer is thinner over substantially vertical surfaces than over substantially horizontal surfaces, forming a mask over a first one of the NFET and the PFET, removing the first stressed silicon nitride layer over a second one of the NFET and the PFET, and forming a second stressed silicon nitride layer over the second one of the NFET and the PFET. The sacrificial layer prevents undercutting and forming of an undesirable residual spacer during removal of the first-deposited stressed layer.
摘要翻译：公开了用于形成双应力层的方法，使得防止第一沉积应力层的底切和不期望的剩余间隔物。在一个实施例中，一种方法包括在NFET和PFET之上形成第一应力氮化硅层，在第一应力氮化硅层上形成牺牲层，使得牺牲层在基本垂直的表面上比在基本水平的表面上更薄，形成在NFET和PFET中的第一个上方的掩模，在NFET和PFET的第二个上去除第一受应力氮化硅层，并且在NFET和PFET的第二个上形成第二应力氮化硅层。牺牲层防止在去除第一次沉积的应力层期间底切和形成不期望的剩余间隔物。

3. 发明申请

US20150311319A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150311319A1
公开(公告)日：2015-10-29
申请号：US14406904
申请日：2012-08-17
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Chao Zhao , Tianchun Ye
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Chao Zhao , Tianchun Ye
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/785 , H01L29/7855
摘要： One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.
摘要翻译：本发明的一个实施例提供了一种用于制造半导体结构的方法，其包括：在半导体衬底上形成栅极叠层并去除位于栅极叠层两侧的衬底的部分; 在所述栅极堆叠的侧壁上以及在所述栅极堆叠下的所述衬底的所述部分的侧壁上形成侧壁间隔物; 在所述栅极堆叠的两侧上在所述衬底的部分中形成掺杂区域，以及形成覆盖整个半导体结构的第一介电层; 选择性地去除所述栅极堆叠的部分和所述第一介电层的部分以形成沟道区域开口和源极/漏极区域开口; 在沟道区域开口的侧壁上形成高K电介质层; 并且实现外延工艺以形成跨越沟道区域开口和源极/漏极区域开口的连续翅片结构。

4. 发明授权

US08895403B2 Transistor, method for fabricating the transistor, and semiconductor device comprising the transistor 有权
标题翻译：晶体管，晶体管的制造方法以及包括该晶体管的半导体器件
公开(公告)号：US08895403B2
公开(公告)日：2014-11-25
申请号：US13698276
申请日：2011-11-30
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L21/00 , H01L21/02 , H01L27/088 , H01L21/8238 , H01L21/84 , H01L27/12
CPC分类号： H01L21/02107 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/088 , H01L27/1203
摘要： A transistor, a method for fabricating a transistor, and a semiconductor device comprising the transistor are disclosed in the present invention. The method for fabricating a transistor may comprise: providing a substrate and forming a first insulating layer on the substrate; defining a first device area on the first insulating layer; forming a spacer surrounding the first device area on the first insulating layer; defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; and forming transistor structures in the first and second device area, respectively. The method for fabricating a transistor of the present invention greatly reduces the space required for isolation, significantly decreases the process complexity, and greatly reduces fabricating cost.
摘要翻译：在本发明中公开了晶体管，晶体管的制造方法以及包括该晶体管的半导体器件。制造晶体管的方法可以包括：提供衬底并在衬底上形成第一绝缘层; 限定所述第一绝缘层上的第一器件区域; 在所述第一绝缘层上形成围绕所述第一器件区域的间隔物; 在所述第一绝缘层上限定第二器件区域，其中所述第二器件区域通过所述间隔物与所述第一器件区域隔离; 以及分别在第一和第二器件区域中形成晶体管结构。本发明的晶体管的制造方法大大降低了隔离所需的空间，显着地降低了工艺的复杂性，大大降低了制造成本。

5. 发明授权

US08846488B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08846488B2
公开(公告)日：2014-09-30
申请号：US13578598
申请日：2011-11-30
申请人： Qingqing Liang , Huaxiang Yin , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huaxiang Yin , Huicai Zhong , Huilong Zhu
IPC分类号： H01L21/76 , H01L29/78 , H01L21/762 , H01L21/265
CPC分类号： H01L21/76224 , H01L21/26506 , H01L29/7842 , H01L29/7847
摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device.
摘要翻译：本发明涉及半导体器件及其制造方法。根据本发明的实施例的半导体器件可以包括：衬底; 位于所述基板上的器件区域; 以及至少一个应力引入区域，其通过隔离结构从所述器件区域分离，其中所述应力引入所述至少一个应力引入区域的至少一部分，其中所述应力引入所述至少一个应力的至少一部分引入区域通过利用激光照射包含在至少一个应力导入区域中的非晶化部分以使非晶化部分重结晶而产生。根据本发明的实施例的半导体器件以更简单的方式产生应力，从而提高器件的性能。

6. 发明申请

US20130221329A1 Graphene Device 审中-公开
标题翻译：石墨烯装置
公开(公告)号：US20130221329A1
公开(公告)日：2013-08-29
申请号：US13582431
申请日：2012-03-29
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Zhi Jin , Xinyu Liu , Tianchun Ye
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Zhi Jin , Xinyu Liu , Tianchun Ye
IPC分类号： H01L29/66
CPC分类号： H01L29/66977 , B82Y10/00 , H01L29/0665 , H01L29/1606 , H01L29/778
摘要： An embodiment of the invention discloses a graphene device comprising a plurality of graphene channels and a gate, wherein one end of all the graphene channels is connected to one terminal, all the graphene channels are in contact with and electrically connected with the gate, and the angles between the graphene channels and the gate are mutually different. Due to a different incident wave angle for a different graphene channel, each of the graphene channels has a different tunneling probability, each of the graphene channels has a different conduction condition, and the graphene device may be used as a device such as a multiplexer or a demultiplexer, etc.
摘要翻译：本发明的实施例公开了一种石墨烯装置，其包括多个石墨烯通道和一个浇口，其中所有石墨烯通道的一端连接到一个端子，所有的石墨烯通道与浇口接触并与门电连接，石墨烯通道和栅极之间的角度是相互不同的。由于不同石墨烯通道的不同的入射波角，每个石墨烯通道具有不同的隧道概率，每个石墨烯通道具有不同的导电条件，并且石墨烯装置可以用作诸如多路复用器或解复用器等

7. 发明申请

US20130200456A1 Semiconductor Substrate, Integrated Circuit Having the Semiconductor Substrate, and Methods of Manufacturing the Same 有权
标题翻译：半导体基板，具有半导体基板的集成电路及其制造方法
公开(公告)号：US20130200456A1
公开(公告)日：2013-08-08
申请号：US13696995
申请日：2011-11-29
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin , Huicai Zhong
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin , Huicai Zhong
IPC分类号： H01L27/12 , H01L27/092 , H01L21/762
CPC分类号： H01L27/12 , H01L21/743 , H01L21/762 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/78648 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same. The semiconductor substrate for use in an integrated circuit comprising transistors having back-gates according to the present invention comprises: a semiconductor base layer; a first insulating material layer on the semiconductor base layer; a first conductive material layer on the first insulating material layer; a second insulating material layer on the first conductive material layer; a second conductive material layer on the second insulating material layer; an insulating buried layer on the second conductive material layer; and a semiconductor layer on the insulating buried layer, wherein at least one first conductive via is provided between the first conductive material layer and the second conductive material layer to penetrate through the second insulating material layer so as to connect the first conductive material layer with the second conductive material layer, the position of each of the first conductive vias being defined by a region in which a corresponding one of a first group of transistors is to be formed.
摘要翻译：本发明涉及半导体衬底，具有半导体衬底的集成电路及其制造方法。根据本发明的包括具有背栅的晶体管的集成电路中使用的半导体衬底包括：半导体基底层; 半导体基底层上的第一绝缘材料层; 第一绝缘材料层上的第一导电材料层; 在所述第一导电材料层上的第二绝缘材料层; 在所述第二绝缘材料层上的第二导电材料层; 第二导电材料层上的绝缘掩埋层; 以及在所述绝缘埋层上的半导体层，其中，在所述第一导电材料层和所述第二导电材料层之间设置有至少一个第一导电通孔，以穿透所述第二绝缘材料层，以将所述第一导电材料层与第二导电材料层，每个第一导电通孔的位置由要形成第一组晶体管中的对应一个的区域限定。

8. 发明授权

US08492210B2 Transistor, semiconductor device comprising the transistor and method for manufacturing the same 有权
标题翻译：晶体管，包括晶体管的半导体器件及其制造方法
公开(公告)号：US08492210B2
公开(公告)日：2013-07-23
申请号：US13144906
申请日：2011-02-25
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong
IPC分类号： H01L21/84
CPC分类号： H01L29/78648 , H01L21/8213 , H01L21/8252 , H01L21/84 , H01L27/0605 , H01L27/1203 , H01L29/66545 , H01L29/66628
摘要： The invention relates to a transistor, a semiconductor device comprising the transistor and manufacturing methods for the transistor and the semiconductor device. The transistor according to the invention comprises: a substrate comprising at least a base layer, a first semiconductor layer, an insulating layer and a second semiconductor layer stacked sequentially; a gate stack formed on the second semiconductor layer; a source region and a drain region located on both sides of the gate stack respectively; a back gate comprising a back gate dielectric and a back gate electrode formed by the insulating layer and the first semiconductor layer, respectively; and a back gate contact formed on a portion of the back gate electrode. The back gate contact comprises an epitaxial part raised from the surface of the back gate electrode, and each of the source region and the drain region comprises an epitaxial part raised from the surface of the second semiconductor layer. As compared to a conventional transistor, the manufacturing process of the transistor of the invention is simplified and the cost of manufacture is reduced.
摘要翻译：本发明涉及晶体管，包括晶体管的半导体器件和用于晶体管和半导体器件的制造方法。根据本发明的晶体管包括：至少包括基层，第一半导体层，绝缘层和顺序层叠的第二半导体层的基板; 形成在所述第二半导体层上的栅叠层; 分别位于栅极堆叠的两侧的源极区域和漏极区域; 包括分别由所述绝缘层和所述第一半导体层形成的背栅电介质和背栅电极的背栅; 以及形成在背栅电极的一部分上的背栅极接触。背栅极触点包括从背栅电极的表面凸起的外延部分，源区和漏区中的每一个包括从第二半导体层的表面凸出的外延部。与常规晶体管相比，本发明的晶体管的制造工艺简化，制造成本降低。

9. 发明授权

US08492206B2 Semiconductor device structure and method for manufacturing the same 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US08492206B2
公开(公告)日：2013-07-23
申请号：US13375692
申请日：2011-08-29
申请人： Huicai Zhong , Jun Luo , Qingqing Liang , Huilong Zhu
发明人： Huicai Zhong , Jun Luo , Qingqing Liang , Huilong Zhu
IPC分类号： H01L21/335 , H01L21/70
CPC分类号： H01L21/823431 , H01L21/823475 , H01L27/0886 , H01L27/1211
摘要： A semiconductor device structure and a method for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction crossing the first direction on the semiconductor substrate, the gate line intersecting the fin via a gate dielectric layer; forming a dielectric spacer surrounding the gate line; forming a conductive spacer surrounding the dielectric spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gate electrodes of respective unit devices, and isolated portions of the conductive spacer form contacts of the respective unit devices.
摘要翻译：公开了一种半导体器件结构及其制造方法。在一个实施例中，所述方法包括：在半导体衬底上沿第一方向形成翅片; 在半导体衬底上与第一方向交叉的第二方向上形成栅极线，栅极线经由栅极电介质层与鳍状物相交; 形成围绕所述栅极线的介电隔离层; 形成围绕所述电介质间隔物的导电间隔物; 以及在预定区域执行器件间电隔离，其中栅极线的隔离部分形成各个单元器件的栅电极，并且导电间隔物的隔离部分形成各个单元器件的接触。

10. 发明申请

US20130093041A1 Semiconductor Device and Method for Manufacturing the Same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20130093041A1
公开(公告)日：2013-04-18
申请号：US13578598
申请日：2011-11-30
申请人： Qingqing Liang , Huaxiang Yin , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huaxiang Yin , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/26506 , H01L29/7842 , H01L29/7847
摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device.
摘要翻译：本发明涉及半导体器件及其制造方法。根据本发明的实施例的半导体器件可以包括：衬底; 位于所述基板上的器件区域; 以及至少一个应力引入区域，其通过隔离结构从所述器件区域分离，其中所述应力引入所述至少一个应力引入区域的至少一部分，其中所述应力引入所述至少一个应力的至少一部分引入区域通过利用激光照射包含在至少一个应力导入区域中的非晶化部分以使非晶化部分重结晶而产生。根据本发明的实施例的半导体器件以更简单的方式产生应力，从而提高器件的性能。

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