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    • 1. 发明申请
    • HIGH-EFFICIENCY ALL-DIGITAL TRANSMITTER
    • 高效全数字发射器
    • US20110176636A1
    • 2011-07-21
    • US12690870
    • 2010-01-20
    • Hua WangToru MatsuuraGregoire Ie Grand de MerceyPaul Cheng-Po LiangKoji TakinamiRichard W. D. Booth
    • Hua WangToru MatsuuraGregoire Ie Grand de MerceyPaul Cheng-Po LiangKoji TakinamiRichard W. D. Booth
    • H04L27/12
    • H04L27/36H03D7/165
    • A low cost high-efficiency all-digital transmitter using all-digital power amplifiers (“DPA”) and various mapping techniques to generate an output signal, which substantially reproduces a baseband signal at a carrier frequency. A baseband signal generator generates a baseband signal which is quantized by a signal processor using a quantization map. A DPA control mapper outputs control signals to phase selectors using the quantized signal and a quantization table. Each phase selector receives one of the control signals and outputs a waveform at a carrier frequency with a phase corresponding to the control signals, or an inactive signal. Each DPA in a DPA array has an assigned weight, receives one of the waveforms from the phase selectors, and outputs a power signal according to the weight of the DPA and the phase of the received waveform. The combined power signal substantially reproduces the baseband signal at the carrier frequency.
    • 使用全数字功率放大器(“DPA”)和各种映射技术的低成本高效全数字发射机产生输出信号,其基本上以载波频率再现基带信号。 基带信号发生器生成使用量化映射由信号处理器量化的基带信号。 DPA控制映射器使用量化信号和量化表将控制信号输出到相位选择器。 每个相位选择器接收一个控制信号,并以与控制信号相对应的相位的载波频率或无效信号输出波形。 DPA阵列中的每个DPA具有分配的权重,从相位选择器接收波形之一,并根据DPA的权重和接收波形的相位输出功率信号。 组合功率信号基本上以载波频率再现基带信号。
    • 2. 发明授权
    • High-efficiency all-digital transmitter
    • 高效全数字发射机
    • US08385469B2
    • 2013-02-26
    • US12690870
    • 2010-01-20
    • Hua WangToru MatsuuraGregoire le Grand de MerceyPaul Cheng-Po LiangKoji TakinamiRichard W. D. Booth
    • Hua WangToru MatsuuraGregoire le Grand de MerceyPaul Cheng-Po LiangKoji TakinamiRichard W. D. Booth
    • H03C3/00
    • H04L27/36H03D7/165
    • A low cost high-efficiency all-digital transmitter using all-digital power amplifiers (“DPA”) and various mapping techniques to generate an output signal, which substantially reproduces a baseband signal at a carrier frequency. A baseband signal generator generates a baseband signal which is quantized by a signal processor using a quantization map. A DPA control mapper outputs control signals to phase selectors using the quantized signal and a quantization table. Each phase selector receives one of the control signals and outputs a waveform at a carrier frequency with a phase corresponding to the control signals, or an inactive signal. Each DPA in a DPA array has an assigned weight, receives one of the waveforms from the phase selectors, and outputs a power signal according to the weight of the DPA and the phase of the received waveform. The combined power signal substantially reproduces the baseband signal at the carrier frequency.
    • 使用全数字功率放大器(DPA)和各种映射技术的低成本高效率全数字发射机来产生输出信号,其基本上以载波频率再现基带信号。 基带信号发生器生成使用量化映射由信号处理器量化的基带信号。 DPA控制映射器使用量化信号和量化表将控制信号输出到相位选择器。 每个相位选择器接收一个控制信号,并以与控制信号相对应的相位的载波频率或无效信号输出波形。 DPA阵列中的每个DPA具有分配的权重,从相位选择器接收波形之一,并根据DPA的权重和接收波形的相位输出功率信号。 组合功率信号基本上以载波频率再现基带信号。
    • 10. 发明授权
    • Method and system for a glitch correction in an all digital phase lock loop
    • 全数字锁相环中毛刺校正的方法和系统
    • US08222939B2
    • 2012-07-17
    • US12838754
    • 2010-07-19
    • Koji TakinamiRichard StrandbergPaul Cheng-Po Liang
    • Koji TakinamiRichard StrandbergPaul Cheng-Po Liang
    • H03L7/06
    • H03L7/16H03L2207/50
    • The present invention relates to a method and system for glitch correction in an all digital phase lock loop. An all digital phase lock loop can include a phase error signal generation unit, a multi-phase oscillator, a glitch correction unit, and a phase to digital converter. The phase to digital converter receives a multi-phase signal from the multi-phase oscillator and generates a phase signal. The error signal generation unit receives the phase signal and a reference phase signal and generates a phase error signal, which is fed to the glitch correction unit. The glitch correction unit removes the glitches in the phase error signal by a portion of the phase error signal. The phase lock loop can also include a phase rotator and a calibration block. The calibration block instructs the phase rotator to rotate the multi-phase signal by the phase rotation which generates the minimum number of glitches.
    • 本发明涉及一种全数字锁相环中毛刺校正的方法和系统。 全数字锁相环可以包括相位误差信号生成单元,多相位振荡器,毛刺校正单元和相位数字转换器。 相数转换器从多相振荡器接收多相信号并产生相位信号。 误差信号发生单元接收相位信号和参考相位信号,并产生馈送到毛刺校正单元的相位误差信号。 毛刺校正单元通过相位误差信号的一部分去除相位误差信号中的毛刺。 锁相环还可以包括相位旋转器和校准块。 校准块指示相位旋转器通过相位旋转旋转多相信号,该相位旋转产生最小数量的毛刺。