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    • 3. 发明授权
    • Method to monitor critical dimension of IC interconnect
    • 监测IC互连关键尺寸的方法
    • US07376920B2
    • 2008-05-20
    • US11398980
    • 2006-04-06
    • Hua QianChing Thiam Chung
    • Hua QianChing Thiam Chung
    • G06F9/45G06F17/50G01R31/08G01R31/02G01R27/00G01R13/00
    • G01R31/2853
    • An example method of monitoring and measuring the line width of interconnects comprising the following steps. First, we measure an I-V profile of a sample interconnect structure to obtain a sample I-V profile. The I-V profile is comprised of leakage current measurements at two or more voltages. The sample interconnect structure is comprised of spaced lines having a line spacing. Next we compare the sample I-V profile with a reference I-V profile at a reference line spacing to determine if sample interconnect structure is not defective. If the sample I-V profile is similar to the reference I-V profile, then leakage currents for the sample interconnect structure are derived from the I-V profiles at a selected voltages. Then we calculate the line spacing of the sample interconnect structure using the sample I-V profile.
    • 监视和测量互连线宽的示例方法,包括以下步骤。 首先,我们测量样品互连结构的I-V轮廓以获得样品I-V轮廓。 I-V曲线由两个或多个电压下的漏电流测量组成。 样品互连结构由具有线间隔的间隔线组成。 接下来,我们将样本I-V剖面与参考线间距的参考I-V剖面进行比较,以确定样本互连结构是否没有缺陷。 如果样品I-V剖面图与参考I-V剖面相似,则样品互连结构的漏电流在选定电压下从I-V剖面得出。 然后我们使用样品I-V曲线计算样品互连结构的线间距。
    • 4. 发明授权
    • Channel decoding method and decoder for tail-biting codes
    • 通道解码方法和解码器,用于尾码
    • US09083385B2
    • 2015-07-14
    • US13809932
    • 2012-03-19
    • Xiaotao WangHua QianJing XuHao HuangYang YangFang Wang
    • Xiaotao WangHua QianJing XuHao HuangYang YangFang Wang
    • H03M13/03H03M13/23H03M13/37H03M13/41H03M13/00H03M13/15
    • H03M13/23H03M13/1505H03M13/3738H03M13/413H03M13/6505H03M13/6525
    • A channel decoding method and decoder are disclosed. The decoding method is based on a Circular Viterbi Algorithm (CVA), rules out impossible initial states one by one through iterations according the received soft information sequence, and finally finds the global optimal tail-biting path. In the present invention, all impossible iterations are ruled out through multiple iterations, and only the initial state having most likelihood with the received sequence survives. The algorithm is finally convergent to an optimal tail-biting path to be output. In addition, the method also updates a metric of a maximum likelihood tail-biting path (MLTBP) or rules out impossible initial states through the obtained surviving tail-biting path, thereby effectively solving the problem that the algorithm is not convergent due to a circular trap, providing a practical optimal decoding algorithm for a tail-biting convolutional code, reducing the complexity of an existing decoding scheme, and saving the storage space.
    • 公开了一种信道解码方法和解码器。 解码方法基于循环维特比算法(CVA),根据接收到的软信息序列逐个排除不可能的初始状态,最终找到全局最优尾巴路径。 在本发明中,通过多次迭代排除所有不可能的迭代,并且只有具有接收序列的最可能性的初始状态才能存活。 该算法最终收敛到要输出的最佳尾巴路径。 另外,该方法还通过所获得的幸存尾巴路径来更新最大似然尾巴路径(MLTBP)的度量或者排除不可能的初始状态,从而有效地解决了算法由于循环而不会收敛的问题 陷阱,为尾部卷积码提供实用的最佳解码算法,降低了现有解码方案的复杂度,并节省了存储空间。
    • 5. 发明申请
    • Method to monitor critical dimension of IC interconnect
    • 监测IC互连关键尺寸的方法
    • US20070247167A1
    • 2007-10-25
    • US11398980
    • 2006-04-06
    • Hua QianChing Chung
    • Hua QianChing Chung
    • G01R31/02
    • G01R31/2853
    • An example method of monitoring and measuring the line width of interconnects comprising the following steps. First, we measure an I-V profile of a sample interconnect structure to obtain a sample I-V profile. The I-V profile is comprised of leakage current measurements at two or more voltages. The sample interconnect structure is comprised of spaced lines having a line spacing. Next we compare the sample I-V profile with a reference I-V profile at a reference line spacing to determine if sample interconnect structure is not defective. If the sample I-V profile is similar to the reference I-V profile, then leakage currents for the sample interconnect structure are derived from the I-V profiles at a selected voltages. Then we calculate the line spacing of the sample interconnect structure using the sample I-V profile.
    • 监视和测量互连线宽的示例方法,包括以下步骤。 首先,我们测量样品互连结构的I-V轮廓以获得样品I-V轮廓。 I-V曲线由两个或多个电压下的漏电流测量组成。 样品互连结构由具有线间隔的间隔线组成。 接下来,我们将样本I-V剖面与参考线间距的参考I-V剖面进行比较,以确定样本互连结构是否没有缺陷。 如果样品I-V剖面图与参考I-V剖面相似,则样品互连结构的漏电流在选定电压下从I-V剖面得出。 然后我们使用样品I-V曲线计算样品互连结构的线间距。
    • 6. 发明授权
    • Flexural pivot for rotary disc drive actuator
    • 用于旋转磁盘驱动器执行器的弯曲枢轴
    • US06963472B2
    • 2005-11-08
    • US09894480
    • 2001-06-27
    • Zhimin HeGuoxiao GuoHua QianEngHong Ong
    • Zhimin HeGuoxiao GuoHua QianEngHong Ong
    • G11B5/54G11B5/55G11B21/16
    • G11B5/5521
    • The present invention provides for a flexural pivot that can be fitted within a cavity of an actuator. The pivot includes a first member that can be coupled to the wall defining the cavity and a second member that can be mounted to the disc drive housing component of the disc drive. At least two leaves join external surfaces of the first member to the second member.The present invention offers a flexural pivot that can be easily incorporated with rotary actuators traditionally designed for use with a ball bearing pivot cartridge. In addition, it avoids the difficulties encountered by conventional designs when trying to assemble intersecting flat springs within a cylindrical sleeve. Furthermore, in comparison with conventional flexural pivots that are located outside the actuator body, the present invention provides a compact pivot that can be mounted substantially in a cavity of the actuator body such that the center of rotation of the actuator is located nearer the center of mass.
    • 本发明提供了一种可以安装在致动器的空腔内的弯曲枢轴。 该枢轴包括可连接到限定空腔的壁的第一构件和可安装到盘驱动器的盘驱动器壳体部件的第二构件。 至少两个叶片将第一构件的外表面连接到第二构件。 本发明提供一种弯曲枢轴,其可以容易地结合有传统上设计用于与球轴承枢轴筒一起使用的旋转致动器。 此外,它避免了当试图在圆柱形套筒内组装交叉的平面弹簧时常规设计遇到的困难。 此外,与位于致动器主体外部的常规弯曲枢轴相比,本发明提供了一种紧凑的枢轴,其可以基本上安装在致动器本体的空腔中,使得致动器的旋转中心位于 质量
    • 7. 发明申请
    • CHANNEL DECODING METHOD AND DECODER FOR TAIL-BITING CODES
    • 信道解码方法和解码器
    • US20130111305A1
    • 2013-05-02
    • US13809932
    • 2012-03-19
    • Xiaotao WangHua QianJing XuHao HuangYang YangFang Wang
    • Xiaotao WangHua QianJing XuHao HuangYang YangFang Wang
    • H03M13/23
    • H03M13/23H03M13/1505H03M13/3738H03M13/413H03M13/6505H03M13/6525
    • A channel decoding method and decoder are disclosed. The decoding method is based on a Circular Viterbi Algorithm (CVA), rules out impossible initial states one by one through iterations according the received soft information sequence, and finally finds the global optimal tail-biting path. In the present invention, all impossible iterations are ruled out through multiple iterations, and only the initial state having most likelihood with the received sequence survives. The algorithm is finally convergent to an optimal tail-biting path to be output. In addition, the method also updates a metric of a maximum likelihood tail-biting path (MLTBP) or rules out impossible initial states through the obtained surviving tail-biting path, thereby effectively solving the problem that the algorithm is not convergent due to a circular trap, providing a practical optimal decoding algorithm for a tail-biting convolutional code, reducing the complexity of an existing decoding scheme, and saving the storage space.
    • 公开了一种信道解码方法和解码器。 解码方法基于循环维特比算法(CVA),根据接收到的软信息序列逐个排除不可能的初始状态,最终找到全局最优尾巴路径。 在本发明中,通过多次迭代排除所有不可能的迭代,并且只有具有接收序列的最可能性的初始状态才能存活。 该算法最终收敛到要输出的最佳尾巴路径。 另外,该方法还通过所获得的幸存尾巴路径来更新最大似然尾巴路径(MLTBP)的度量或者排除不可能的初始状态,从而有效地解决了算法由于循环而不会收敛的问题 陷阱,为尾部卷积码提供实用的最佳解码算法,降低了现有解码方案的复杂度,并节省了存储空间。
    • 9. 发明授权
    • Digital Predistortion for nonlinear RF power amplifiers
    • 非线性射频功率放大器的数字预失真
    • US08498591B1
    • 2013-07-30
    • US12860108
    • 2010-08-20
    • Hua QianSongping WuDaxiao Yu
    • Hua QianSongping WuDaxiao Yu
    • H04B1/04H03C1/62
    • H04L1/0035H03F1/3241H04B1/0475H04B2001/0425
    • Systems and techniques relating to wireless communications are described. A described technique includes generating a digital transmit signal, receiving a digital receive signal, storing signal samples, the signal samples including transmit samples based on the digital transmit signal and receive samples based on the digital receive signal, causing, in a predistortion training mode, the digital receive signal to be based on an amplified analog version of the digital transmit signal, where the amplified analog version is produced by a power amplifier having one or more nonlinear characteristics, determining a synchronization offset value to align the transmit samples with the receive samples, determining one or more power normalization parameter values to normalize a power of the digital receive signal with respect to the digital transmit signal, estimating predistortion parameter values, and using the predistortion parameter values to predistort digital signals to compensate for the one or more nonlinear characteristics of the power amplifier. Estimating predistortion parameter values can include using information comprising the transmit samples, the receive samples, the synchronization offset value, and the one or more power normalization parameter values.
    • 描述与无线通信相关的系统和技术。 所描述的技术包括产生数字发送信号,接收数字接收信号,存储信号采样,信号样本包括基于数字发送信号的发送采样,并且基于数字接收信号接收采样,以预失真训练模式, 所述数字接收信号将基于所述数字发射信号的放大的模拟版本,其中所述放大的模拟版本由具有一个或多个非线性特性的功率放大器产生,确定同步偏移值以使所述发射样本与所述接收样本 ,确定一个或多个功率归一化参数值以相对于所述数字发射信号归一化所述数字接收信号的功率,估计预失真参数值,以及使用所述预失真参数值来预失真数字信号以补偿所述一个或多个非线性特性 的功率放大器。 估计预失真参数值可以包括使用包括发送样本,接收样本,同步偏移值和一个或多个功率归一化参数值的信息。