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1. 发明授权

US06713335B2 Method of self-aligning a damascene gate structure to isolation regions 失效
标题翻译：将镶嵌栅极结构自对准到隔离区域的方法
公开(公告)号：US06713335B2
公开(公告)日：2004-03-30
申请号：US10225805
申请日：2002-08-22
申请人： Daniel Yen , Ching-Thiam Chung , Wei Hua Cheng , Chester Nieh , Tong Boon Lee
发明人： Daniel Yen , Ching-Thiam Chung , Wei Hua Cheng , Chester Nieh , Tong Boon Lee
IPC分类号： H01L218238
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28097 , H01L21/28167 , H01L21/76229 , H01L21/823878 , H01L29/495 , H01L29/4975 , H01L29/51 , H01L29/517 , H01L29/66492 , H01L29/66545 , H01L29/66553 , H01L29/6659
摘要： A process for fabricating a CMOS device in which conductive gate structures are defined self-aligned to shallow trench isolation (STI), regions, without using a photolithographic procedure, has been developed. The process features definition of shallow trench openings in regions of a semiconductor substrate not covered by dummy gate structures, or by silicon oxide spacers located on sides of the dummy gate structures. Filling of the shallow trench openings with silicon oxide, and removal of the dummy gate structures, result in STI regions comprised of filled shallow trench openings, overlying silicon oxide shapes, and silicon oxide sidewall spacers on the sides of the overlying silicon oxide shapes. Formation of silicon nitride spacers on the sides of the STI regions, is followed by deposition of a high k gate insulator layer and of a conductive gate structure, with the conductive gate structure formed self-aligned to the STI regions.
摘要翻译：已经开发了制造CMOS器件的方法，其中导电栅结构被限定为与浅沟槽隔离（STI）区域自对准，而不使用光刻工艺。该工艺的特征是在未被虚拟栅极结构覆盖的半导体衬底的区域中或通过位于虚拟栅极结构的侧面上的氧化硅间隔区的浅沟槽开口的定义。用氧化硅填充浅沟槽开口和去除虚拟栅极结构导致STI区域由覆盖的氧化硅形状的填充的浅沟槽开口和覆盖的氧化硅形状的侧面上的氧化硅侧壁间隔件组成。在STI区域的侧面上形成氮化硅间隔物，随后沉积高k栅极绝缘体层和导电栅极结构，导电栅极结构与STI区域自对准。

2. 发明授权

US07376920B2 Method to monitor critical dimension of IC interconnect 有权
标题翻译：监测IC互连关键尺寸的方法
公开(公告)号：US07376920B2
公开(公告)日：2008-05-20
申请号：US11398980
申请日：2006-04-06
申请人： Hua Qian , Ching Thiam Chung
发明人： Hua Qian , Ching Thiam Chung
IPC分类号： G06F9/45 , G06F17/50 , G01R31/08 , G01R31/02 , G01R27/00 , G01R13/00
CPC分类号： G01R31/2853
摘要： An example method of monitoring and measuring the line width of interconnects comprising the following steps. First, we measure an I-V profile of a sample interconnect structure to obtain a sample I-V profile. The I-V profile is comprised of leakage current measurements at two or more voltages. The sample interconnect structure is comprised of spaced lines having a line spacing. Next we compare the sample I-V profile with a reference I-V profile at a reference line spacing to determine if sample interconnect structure is not defective. If the sample I-V profile is similar to the reference I-V profile, then leakage currents for the sample interconnect structure are derived from the I-V profiles at a selected voltages. Then we calculate the line spacing of the sample interconnect structure using the sample I-V profile.
摘要翻译：监视和测量互连线宽的示例方法，包括以下步骤。首先，我们测量样品互连结构的I-V轮廓以获得样品I-V轮廓。 I-V曲线由两个或多个电压下的漏电流测量组成。样品互连结构由具有线间隔的间隔线组成。接下来，我们将样本I-V剖面与参考线间距的参考I-V剖面进行比较，以确定样本互连结构是否没有缺陷。如果样品I-V剖面图与参考I-V剖面相似，则样品互连结构的漏电流在选定电压下从I-V剖面得出。然后我们使用样品I-V曲线计算样品互连结构的线间距。

3. 发明授权

US06743694B2 Method of wafer marking for multi-layer metal processes 失效
标题翻译：多层金属工艺的晶圆标记方法
公开(公告)号：US06743694B2
公开(公告)日：2004-06-01
申请号：US10135045
申请日：2002-04-30
申请人： Ching Thiam Chung , Kay Jin Lee
发明人： Ching Thiam Chung , Kay Jin Lee
IPC分类号： H01L2176
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A new method of forming a laser mark without damage to the wafer surface is described. A pad oxide layer is formed on a silicon wafer. A nitride layer is deposited overlying the pad oxide layer. A first trench is laser cut through the nitride layer and the pad oxide layer into the silicon wafer. The trench is etched to a second depth wherein the nitride layer is used as a hard mask and wherein the trench forms an identification mark.
摘要翻译：描述了形成激光标记而不损坏晶片表面的新方法。在硅晶片上形成衬垫氧化物层。在衬垫氧化物层上沉积氮化物层。激光切割第一沟槽通过氮化物层和衬垫氧化物层进入硅晶片。将沟槽蚀刻到第二深度，其中氮化物层用作硬掩模，并且其中沟槽形成识别标记。

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