专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070257339A1 SHIELD STRUCTURES 审中-公开
标题翻译：屏蔽结构
公开(公告)号：US20070257339A1
公开(公告)日：2007-11-08
申请号：US11382202
申请日：2006-05-08
申请人： Hsien-Wei Chen , Victor Chang , Tzu-Jin Yeh , Shu-Ying Cho , Keh-Jeng Chang , Kwang-Leei Young
发明人： Hsien-Wei Chen , Victor Chang , Tzu-Jin Yeh , Shu-Ying Cho , Keh-Jeng Chang , Kwang-Leei Young
IPC分类号： H01L23/62
CPC分类号： H01L23/552 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H05K1/0219 , H05K1/0298 , H05K2201/09236 , H05K2201/09618 , H01L2924/00
摘要： Shield structures are provided. A first and second shield lines are formed over a substrate and coupled with a first voltage. A conductive line is formed between the first and the second shield lines, and coupled with a second voltage. The first shield layer is formed over the substrate and coupled to the first and the second shield lines via at least one first conductive structure.
摘要翻译：提供盾构结构。第一和第二屏蔽线形成在衬底上并与第一电压耦合。在第一和第二屏蔽线之间形成导线，并与第二电压耦合。第一屏蔽层形成在衬底上并且经由至少一个第一导电结构耦合到第一屏蔽线和第二屏蔽线。

2. 发明授权

US06643831B2 Method and system for extraction of parasitic interconnect impedance including inductance 有权
公开(公告)号：US06643831B2
公开(公告)日：2003-11-04
申请号：US10057165
申请日：2002-01-24
申请人： Keh-Jeng Chang , Li-Fu Chang , Robert G. Mathews , Martin G. Walker
发明人： Keh-Jeng Chang , Li-Fu Chang , Robert G. Mathews , Martin G. Walker
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.

3. 发明申请

US20110168995A1 Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits 有权
标题翻译：超大规模集成电路的精确电容测量
公开(公告)号：US20110168995A1
公开(公告)日：2011-07-14
申请号：US13015117
申请日：2011-01-27
申请人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
发明人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
IPC分类号： H01L23/544
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.
摘要翻译：提供了用于测量集成电路中的接触和通过寄生电容的测试结构和方法。通过从测量结果中消除不被测量的电容，提高了接触和通孔电容测量的精度。电容是在必须测量的接触或电容的目标测试结构上测量的。然后在基本相似的参考测试结构上重复测量，该测试结构不受测量的接触或通过电容。通过使用两个测试结构的电容测量，可以计算待测量的接触和通孔电容。

4. 发明授权

US07772868B2 Accurate capacitance measurement for ultra large scale integrated circuits 有权
标题翻译：超大规模集成电路的精确电容测量
公开(公告)号：US07772868B2
公开(公告)日：2010-08-10
申请号：US11966653
申请日：2007-12-28
申请人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
发明人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
IPC分类号： G01R31/26
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.
摘要翻译：提供了用于测量集成电路中的接触和通过寄生电容的测试结构和方法。通过从测量结果中消除不被测量的电容，提高了接触和通孔电容测量的精度。电容是在必须测量的接触或电容的目标测试结构上测量的。然后在基本相似的参考测试结构上重复测量，该测试结构不受测量的接触或通过电容。通过使用两个测试结构的电容测量，可以计算待测量的接触和通孔电容。

5. 发明申请

US20090002012A1 Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits 有权
标题翻译：超大规模集成电路的精确电容测量
公开(公告)号：US20090002012A1
公开(公告)日：2009-01-01
申请号：US11966653
申请日：2007-12-28
申请人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
发明人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
IPC分类号： G01R31/26 , H01L23/58
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.
摘要翻译：提供了用于测量集成电路中的接触和通过寄生电容的测试结构和方法。通过从测量结果中消除不被测量的电容，提高了接触和通孔电容测量的精度。电容是在必须测量的接触或电容的目标测试结构上测量的。然后在基本相似的参考测试结构上重复测量，该测试结构不受测量的接触或通过电容。通过使用两个测试结构的电容测量，可以计算待测量的接触和通孔电容。

6. 发明授权

US06381730B1 Method and system for extraction of parasitic interconnect impedance including inductance 有权
标题翻译：用于提取包括电感的寄生互连阻抗的方法和系统
公开(公告)号：US06381730B1
公开(公告)日：2002-04-30
申请号：US09350966
申请日：1999-07-09
申请人： Keh-Jeng Chang , Li-Fu Chang , Robert G. Mathews , Martin G. Walker
发明人： Keh-Jeng Chang , Li-Fu Chang , Robert G. Mathews , Martin G. Walker
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.
摘要翻译：一种新颖的寄生提取系统包括具有用于集成电路的至少一个导电层的参数化电感功能的互连原语库。寄生提取器分析集成电路内所选导体的选定距离内的结构，并使用互连原始库的参数化电感函数确定所选导体的寄生电感值。使用这种寄生提取系统，可以提取包括电感的寄生阻抗用于集成电路布局，从而允许获得集成电路布局的更精确的建模和时序分析。

7. 发明授权

US06312963B1 Methods for determining on-chip interconnect process parameters 有权
公开(公告)号：US06312963B1
公开(公告)日：2001-11-06
申请号：US09245812
申请日：1999-02-04
申请人： Shih-Tsun Alexander Chou , Keh-Jeng Chang , Robert G. Mathews
发明人： Shih-Tsun Alexander Chou , Keh-Jeng Chang , Robert G. Mathews
IPC分类号： G01L2166
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method provides estimations of physical interconnect process parameter values in a process for manufacturing integrated circuits. The method includes fabricating test structures each providing a value of a measurable quantity corresponding to a value within a range of values of the physical interconnect process parameters. In some embodiments, the measured value is used to derive the values of the physical interconnect process parameters, either by a numerical method using a field solver, or by a closed-form solution. The values of physical interconnect process parameters involving physical dimensions are also obtained by measuring photomicrographs obtained using a scanning electron microscope from cross sections of test structures. In some embodiments, a family of test structures corresponding to a range of conductor widths and a range of spacings between conductors are measured.

8. 发明授权

US06311312B1 Method for modeling a conductive semiconductor substrate 有权
标题翻译：导电半导体衬底建模方法
公开(公告)号：US06311312B1
公开(公告)日：2001-10-30
申请号：US09405510
申请日：1999-09-23
申请人： Keh-Jeng Chang , Robert G. Mathews , Li-Fu Chang , Xu Yang
发明人： Keh-Jeng Chang , Robert G. Mathews , Li-Fu Chang , Xu Yang
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： A method models conductive regions of a semiconductor substrate in conjunction with conductors in the interconnect structures above the semiconductor substrate. Such a method allows highly accurate extraction of capacitance in planar (e.g., shallow trench isolation) and non-planar (e.g., thermal oxide isolation) semiconductor structures. This method is particularly applicable to modeling dummy diffusion regions prevalent in shallow trench isolation structures. An area-perimeter approach simplifies calculation of capacitance without using a 3-dimensional electric field solver. A method is also provided for extracting a capacitance associate with a contact, or a connecting conductor between two conductor layers.
摘要翻译：一种方法结合半导体衬底上的互连结构中的导体来模拟半导体衬底的导电区域。这种方法允许在平面（例如浅沟槽隔离）和非平面（例如，热氧化物隔离）半导体结构中高度精确地提取电容。该方法特别适用于对浅沟槽隔离结构中普遍存在的虚拟扩散区进行建模。区域周边方法简化了电容的计算，而不使用3维电场求解器。还提供了一种用于提取与触点或两个导体层之间的连接导体相关联的电容的方法。

9. 发明授权

US07880494B2 Accurate capacitance measurement for ultra large scale integrated circuits 有权
标题翻译：超大规模集成电路的精确电容测量
公开(公告)号：US07880494B2
公开(公告)日：2011-02-01
申请号：US12715739
申请日：2010-03-02
申请人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
发明人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
IPC分类号： G01R31/26
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.
摘要翻译：提供了用于测量集成电路中的接触和通过寄生电容的测试结构和方法。通过从测量结果中消除不被测量的电容，提高了接触和通孔电容测量的精度。电容是在必须测量的接触或电容的目标测试结构上测量的。然后在基本相似的参考测试结构上重复测量，该测试结构不受测量的接触或通过电容。通过使用两个测试结构的电容测量，可以计算待测量的接触和通孔电容。

10. 发明申请

US20100156453A1 Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits 有权
标题翻译：超大规模集成电路的精确电容测量
公开(公告)号：US20100156453A1
公开(公告)日：2010-06-24
申请号：US12715739
申请日：2010-03-02
申请人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
发明人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
IPC分类号： G01R31/26 , G01R27/26
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.
摘要翻译：提供了用于测量集成电路中的接触和通过寄生电容的测试结构和方法。通过从测量结果中消除不被测量的电容，提高了接触和通孔电容测量的精度。电容是在必须测量的接触或电容的目标测试结构上测量的。然后在基本相似的参考测试结构上重复测量，该测试结构不受测量的接触或通过电容。通过使用两个测试结构的电容测量，可以计算待测量的接触和通孔电容。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式