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1. 发明授权

US08685820B2 Multiple gate dielectric structures and methods of forming the same 有权
标题翻译：多栅电介质结构及其形成方法
公开(公告)号：US08685820B2
公开(公告)日：2014-04-01
申请号：US13207643
申请日：2011-08-11
申请人： Hsiao-Hui Tseng , Dun-Nian Yaung , Jen-Cheng Liu , Wen-I Hsu , Min-Feng Kao
发明人： Hsiao-Hui Tseng , Dun-Nian Yaung , Jen-Cheng Liu , Wen-I Hsu , Min-Feng Kao
IPC分类号： H01L21/336
CPC分类号： H01L27/14614 , H01L27/14689
摘要： The present disclosure provides for multiple gate dielectric semiconductor structures and methods of forming such structures. In one embodiment, a method of forming a semiconductor structure includes providing a substrate including a pixel array region, an input/output (I/O) region, and a core region. The method further includes forming a first gate dielectric layer over the pixel array region, forming a second gate dielectric layer over the I/O region, and forming a third gate dielectric layer over the core region, wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are each formed to be comprised of a different material and to have a different thickness.
摘要翻译：本公开提供了多栅极电介质半导体结构和形成这种结构的方法。在一个实施例中，形成半导体结构的方法包括提供包括像素阵列区域，输入/输出（I / O）区域和核心区域的衬底。该方法还包括在像素阵列区域上形成第一栅极电介质层，在I / O区域上形成第二栅极电介质层，以及在芯区域上形成第三栅极电介质层，其中第一栅极介电层，第二栅极电介质层栅极电介质层和第三栅极电介质层各自形成为由不同的材料构成并且具有不同的厚度。

2. 发明申请

US20130037890A1 MULTIPLE GATE DIELECTRIC STRUCTURES AND METHODS OF FORMING THE SAME 有权
标题翻译：多栅型电介质结构及其形成方法
公开(公告)号：US20130037890A1
公开(公告)日：2013-02-14
申请号：US13207643
申请日：2011-08-11
申请人： Hsiao-Hui Tseng , Dun-Nian Yaung , Jen-Cheng Liu , Wen-I Hsu , Min-Feng Kao
发明人： Hsiao-Hui Tseng , Dun-Nian Yaung , Jen-Cheng Liu , Wen-I Hsu , Min-Feng Kao
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L27/14614 , H01L27/14689
摘要： The present disclosure provides for multiple gate dielectric semiconductor structures and methods of forming such structures. In one embodiment, a method of forming a semiconductor structure includes providing a substrate including a pixel array region, an input/output (I/O) region, and a core region. The method further includes forming a first gate dielectric layer over the pixel array region, forming a second gate dielectric layer over the I/O region, and forming a third gate dielectric layer over the core region, wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are each formed to be comprised of a different material and to have a different thickness.
摘要翻译：本公开提供了多栅极电介质半导体结构和形成这种结构的方法。在一个实施例中，形成半导体结构的方法包括提供包括像素阵列区域，输入/输出（I / O）区域和核心区域的衬底。该方法还包括在像素阵列区域上形成第一栅极电介质层，在I / O区域上形成第二栅极电介质层，以及在芯区域上形成第三栅极电介质层，其中第一栅极介电层，第二栅极电介质层栅极电介质层和第三栅极电介质层各自形成为由不同的材料构成并且具有不同的厚度。

3. 发明授权

US09048162B2 CMOS image sensors and methods for forming the same 有权
标题翻译： CMOS图像传感器及其形成方法
公开(公告)号：US09048162B2
公开(公告)日：2015-06-02
申请号：US13615071
申请日：2012-09-13
申请人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Hsiao-Hui Tseng , Tzu-Hsuan Hsu
发明人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Hsiao-Hui Tseng , Tzu-Hsuan Hsu
IPC分类号： H01L31/02 , H01L27/146 , H01L31/18 , H01L31/103
CPC分类号： H01L31/18 , H01L27/1461 , H01L27/14621 , H01L27/14627 , H01L27/1464 , H01L27/14689 , H01L31/02 , H01L31/103 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A device includes a diode, which includes a first, a second, and a third doped region in a semiconductor substrate. The first doped region is of a first conductivity type, and has a first impurity concentration. The second doped region is of the first conductivity type, and has a second impurity concentration lower than the first impurity concentration. The second doped region encircles the first doped region. The third doped region is of a second conductivity type opposite the first conductivity type, wherein the third doped region overlaps a portion of the first doped region and a portion of the second doped region.
摘要翻译：一种器件包括二极管，其包括半导体衬底中的第一，第二和第三掺杂区域。第一掺杂区域是第一导电类型，并具有第一杂质浓度。第二掺杂区域是第一导电类型，并且具有低于第一杂质浓度的第二杂质浓度。第二掺杂区域包围第一掺杂区域。第三掺杂区域具有与第一导电类型相反的第二导电类型，其中第三掺杂区域与第一掺杂区域的一部分和第二掺杂区域的一部分重叠。

4. 发明申请

US20130320420A1 CMOS Image Sensors and Methods for Forming the Same 有权
标题翻译： CMOS图像传感器及其形成方法
公开(公告)号：US20130320420A1
公开(公告)日：2013-12-05
申请号：US13615071
申请日：2012-09-13
申请人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Hsiao-Hui Tseng , Tzu-Hsuan Hsu
发明人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Hsiao-Hui Tseng , Tzu-Hsuan Hsu
IPC分类号： H01L31/02 , H01L31/18
CPC分类号： H01L31/18 , H01L27/1461 , H01L27/14621 , H01L27/14627 , H01L27/1464 , H01L27/14689 , H01L31/02 , H01L31/103 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A device includes a diode, which includes a first, a second, and a third doped region in a semiconductor substrate. The first doped region is of a first conductivity type, and has a first impurity concentration. The second doped region is of the first conductivity type, and has a second impurity concentration lower than the first impurity concentration. The second doped region encircles the first doped region. The third doped region is of a second conductivity type opposite the first conductivity type, wherein the third doped region overlaps a portion of the first doped region and a portion of the second doped region.
摘要翻译：一种器件包括二极管，其包括半导体衬底中的第一，第二和第三掺杂区域。第一掺杂区域是第一导电类型，并具有第一杂质浓度。第二掺杂区域是第一导电类型，并且具有低于第一杂质浓度的第二杂质浓度。第二掺杂区域包围第一掺杂区域。第三掺杂区域具有与第一导电类型相反的第二导电类型，其中第三掺杂区域与第一掺杂区域的一部分和第二掺杂区域的一部分重叠。

5. 发明授权

US08513587B2 Image sensor with anti-reflection layer and method of manufacturing the same 有权
标题翻译：具有防反射层的图像传感器及其制造方法
公开(公告)号：US08513587B2
公开(公告)日：2013-08-20
申请号：US13012067
申请日：2011-01-24
申请人： Tzu-Jui Wang , Hsiao-Hui Tseng , Wei-Cheng Hsu , Dun-Nian Yaung , Jen-Cheng Liu
发明人： Tzu-Jui Wang , Hsiao-Hui Tseng , Wei-Cheng Hsu , Dun-Nian Yaung , Jen-Cheng Liu
IPC分类号： H01L27/00 , H01L31/00 , H01L29/80 , H01L21/02
CPC分类号： H01L27/1464 , H01L27/1461 , H01L27/14629
摘要： An image sensor the image sensor comprising an absorption layer disposed on a silicon substrate, the absorption layer having at least one of SiGe or Ge, and an antireflection layer disposed directly thereon.
摘要翻译：图像传感器包括设置在硅衬底上的吸收层，所述吸收层具有SiGe或Ge中的至少一种，以及直接设置在其上的抗反射层。

6. 发明授权

US09165970B2 Back side illuminated image sensor having isolated bonding pads 有权
标题翻译：具有隔离接合垫的背面照明图像传感器
公开(公告)号：US09165970B2
公开(公告)日：2015-10-20
申请号：US13028471
申请日：2011-02-16
申请人： Shuang-Ji Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Wen-De Wang , Hsiao-Hui Tseng
发明人： Shuang-Ji Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Wen-De Wang , Hsiao-Hui Tseng
IPC分类号： H01L27/146
CPC分类号： H01L27/14687 , H01L23/481 , H01L23/525 , H01L24/83 , H01L27/14623 , H01L27/14632 , H01L27/14636 , H01L27/14638 , H01L27/1464 , H01L27/14645 , H01L27/14683 , H01L27/14689
摘要： Provided is an image sensor device. The image sensor device includes having a front side, a back side, and a sidewall connecting the front and back sides. The image sensor device includes a plurality of radiation-sensing regions disposed in the substrate. Each of the radiation-sensing regions is operable to sense radiation projected toward the radiation-sensing region through the back side. The image sensor device includes an interconnect structure that is coupled to the front side of the substrate. The interconnect structure includes a plurality of interconnect layers and extends beyond the sidewall of the substrate. The image sensor device includes a bonding pad that is spaced apart from the sidewall of the substrate. The bonding pad is electrically coupled to one of the interconnect layers of the interconnect structure.
摘要翻译：提供了一种图像传感器装置。图像传感器装置包括具有连接前侧和后侧的前侧，后侧和侧壁。图像传感器装置包括设置在基板中的多个辐射感测区域。每个辐射感测区域可操作以感测通过后侧朝向辐射感测区域投射的辐射。图像传感器装置包括耦合到基板的前侧的互连结构。互连结构包括多个互连层并且延伸超过衬底的侧壁。图像传感器装置包括与衬底的侧壁间隔开的接合焊盘。接合焊盘电连接到互连结构的互连层之一。

7. 发明申请

US20130341692A1 Novel [N] Profile in Si-Ox Interface for CMOS Image Sensor Performance Improvement 审中-公开
标题翻译：用于CMOS图像传感器性能改进的Si-Ox接口中的新型[N]配置文件
公开(公告)号：US20130341692A1
公开(公告)日：2013-12-26
申请号：US13601033
申请日：2012-08-31
申请人： Hsiao-Hui Tseng , Jen-Cheng Liu , Dun-Nian Yaung , Tzu-Hsuan Hsu
发明人： Hsiao-Hui Tseng , Jen-Cheng Liu , Dun-Nian Yaung , Tzu-Hsuan Hsu
IPC分类号： H01L27/146 , H01L21/8238
CPC分类号： H01L27/14603 , H01L27/1463 , H01L27/14643 , H01L29/513 , H01L29/518
摘要： A semiconductor device including first and second isolation regions supported by a substrate, a first array well supported by the first isolation region, the first array well having a first field implant layer embedded therein, the first field implant layer surrounding a first shallow trench isolation region, a second array well supported by the second isolation region, the second array well supporting a doped region and a drain and having a second field implant layer embedded therein, the second field implant layer surrounding a second shallow trench isolation region, a stack of photodiodes disposed in the substrate between the first and second isolation regions, and a gate oxide formed over an uppermost photodiode of the stack of the photodiodes, the gate oxide and a silicon of the uppermost photodiode forming an interface, a nitrogen concentration at the interface offset from a peak nitrogen concentration.
摘要翻译：一种半导体器件，包括由衬底支撑的第一和第二隔离区域，由第一隔离区域良好地支撑的第一阵列，第一阵列阱具有嵌入其中的第一场注入层，第一场注入层围绕第一浅沟槽隔离区域，由第二隔离区域良好支撑的第二阵列，第二阵列阱支撑掺杂区域和漏极，并且具有嵌入其中的第二场注入层，第二场注入层围绕第二浅沟槽隔离区域，一叠光电二极管设置在第一和第二隔离区域之间的衬底中，以及形成在光电二极管的堆叠的最上面的光电二极管上的栅极氧化物，栅极氧化物和最上面的光电二极管的硅形成界面，界面处的氮浓度偏离氮浓度峰值。

8. 发明申请

US20120205769A1 BACK SIDE ILLUMINATED IMAGE SENSOR WITH REDUCED SIDEWALL-INDUCED LEAKAGE 有权
标题翻译：具有降低的侧壁感应泄漏的背面照明图像传感器
公开(公告)号：US20120205769A1
公开(公告)日：2012-08-16
申请号：US13028471
申请日：2011-02-16
申请人： Shuang-Ji Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Wen-De Wang , Hsiao-Hui Tseng
发明人： Shuang-Ji Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Wen-De Wang , Hsiao-Hui Tseng
IPC分类号： H01L31/02 , H01L31/18
CPC分类号： H01L27/14687 , H01L23/481 , H01L23/525 , H01L24/83 , H01L27/14623 , H01L27/14632 , H01L27/14636 , H01L27/14638 , H01L27/1464 , H01L27/14645 , H01L27/14683 , H01L27/14689
摘要： Provided is an image sensor device. The image sensor device includes having a front side, a back side, and a sidewall connecting the front and back sides. The image sensor device includes a plurality of radiation-sensing regions disposed in the substrate. Each of the radiation-sensing regions is operable to sense radiation projected toward the radiation-sensing region through the back side. The image sensor device includes an interconnect structure that is coupled to the front side of the substrate. The interconnect structure includes a plurality of interconnect layers and extends beyond the sidewall of the substrate. The image sensor device includes a bonding pad that is spaced apart from the sidewall of the substrate. The bonding pad is electrically coupled to one of the interconnect layers of the interconnect structure.
摘要翻译：提供了一种图像传感器装置。图像传感器装置包括具有连接前侧和后侧的前侧，后侧和侧壁。图像传感器装置包括设置在基板中的多个辐射感测区域。每个辐射感测区域可操作以感测通过后侧朝向辐射感测区域投射的辐射。图像传感器装置包括耦合到基板的前侧的互连结构。互连结构包括多个互连层并且延伸超过衬底的侧壁。图像传感器装置包括与衬底的侧壁间隔开的接合焊盘。接合焊盘电连接到互连结构的互连层之一。

9. 发明授权

US06656786B2 MIM process for logic-based embedded RAM having front end manufacturing operation 有权
标题翻译：用于具有前端制造操作的基于逻辑的嵌入式RAM的MIM工艺
公开(公告)号：US06656786B2
公开(公告)日：2003-12-02
申请号：US10000896
申请日：2001-11-02
申请人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Tazy-Schiuan Yang
发明人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Tazy-Schiuan Yang
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10814 , H01L27/10894 , H01L28/60 , Y10S977/888
摘要： A method and system for manufacturing an MIM capacitor for utilization with a logic-based embedded DRAM device. At least one transistor, an interlayer dielectric, at least one contact and at least one metal one layer are generally formed on a substrate during a front end manufacturing operation of the capacitor on the substrate. An inter-metal dielectric layer is deposited upon the substrate, followed thereafter by a chemical mechanical polishing operation. Additionally, a lithographic operation is performed upon the substrate. Also, at least one dielectric deposition layer is generally on the substrate, followed thereafter by a chemical mechanical polishing operation and a stop on an oxide layer formed on the substrate. At least one metal two layer may then be formed on substrate and associated layers thereof, thereby resulting in the formation of a capacitor fully compatible with logic-based devices and processes thereof.
摘要翻译：一种制造用于利用基于逻辑的嵌入式DRAM器件的MIM电容器的方法和系统。在基板上的电容器的前端制造操作期间，通常在基板上形成至少一个晶体管，层间电介质，至少一个触点和至少一个金属层。金属介电层沉积在基板上，其后通过化学机械抛光操作。另外，在基板上执行光刻操作。此外，至少一个电介质沉积层通常在衬底上，随后通过化学机械抛光操作和在形成在衬底上的氧化物层上的停止。然后可以在衬底及其相关层上形成至少一个金属二层，从而形成与基于逻辑的器件及其工艺完全兼容的电容器。

10. 发明授权

US06383863B1 Approach to integrate salicide gate for embedded DRAM devices 有权
标题翻译：为嵌入式DRAM设备集成自杀门的方法
公开(公告)号：US06383863B1
公开(公告)日：2002-05-07
申请号：US09963595
申请日：2001-09-27
申请人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Chung-Wei Chang , Kuo-Chyuan Tzeng
发明人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Chung-Wei Chang , Kuo-Chyuan Tzeng
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L21/76889 , H01L21/76897 , H01L27/10873 , H01L27/10888 , H01L28/84 , H01L28/90 , H01L29/66545
摘要： A process for integrating the formation of a salicide layer on DRAM word line structures, and on a bit line contact structure, has been developed. The process features selective etch back of the insulator layers embedding the tapered shaped bit line contact, and the tapered shape capacitor structures, exposing top surface portions of polysilicon word line structures. The selective etch back procedure also results in formation of insulator spacers on the sides of the tapered bit line contact, and capacitor structures, allowing a subsequent salicide procedure to form metal suicide layers only on the exposed top surfaces of the DRAM word line, bit line contact, and capacitor structures.
摘要翻译：已经开发了一种用于将自对准硅化物层形成在DRAM字线结构上以及位线接触结构上的过程。该工艺具有嵌入锥形位线接触件的绝缘体层的选择性回蚀和锥形形状电容器结构，暴露多晶硅字线结构的顶表面部分。选择性回蚀程序还导致在锥形位线接触和电容器结构的侧面上形成绝缘体间隔物，并且允许随后的自对准硅化物程序仅在DRAM字线，位线的暴露的顶表面上形成金属硅化物层接触和电容器结构。

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