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1. 发明授权

US06838714B2 Low leakage diodes, including photodiodes 有权
标题翻译：低漏电二极管，包括光电二极管
公开(公告)号：US06838714B2
公开(公告)日：2005-01-04
申请号：US09780390
申请日：2001-02-12
申请人： Howard E. Rhodes , Werner Juengling , Thomas A. Figura , Steven D. Cummings
发明人： Howard E. Rhodes , Werner Juengling , Thomas A. Figura , Steven D. Cummings
IPC分类号： H01L27/146 , H01L27/148 , H01L29/861 , H01L31/062
CPC分类号： H01L27/14687 , H01L27/14609 , H01L27/14806 , H01L29/8611
摘要： A photodiode for use in an imager having an improved charge leakage. The photodiode has a doped region that is spaced away from the field isolation to minimize charge leakage. A second embodiment of invention provides a second implant to improve charge leakage to the substrate. The photodiodes according to the invention provide improve charge leakage, improved reactions to dark current and an improved signal to noise ratio. Also disclosed are processes for forming the photodiode.
摘要翻译：用于具有改善的电荷泄漏的成像器中的光电二极管。光电二极管具有与场隔离间隔开的掺杂区域，以最小化电荷泄漏。本发明的第二实施例提供了一种第二种植入物，用于改善对衬底的电荷泄漏。根据本发明的光电二极管提供改善电荷泄漏，改善对暗电流的反应和改善的信噪比。还公开了用于形成光电二极管的工艺。

2. 发明授权

US06534335B1 Optimized low leakage diodes, including photodiodes 有权
标题翻译：优化的低漏电二极管，包括光电二极管
公开(公告)号：US06534335B1
公开(公告)日：2003-03-18
申请号：US09358543
申请日：1999-07-22
申请人： Howard E. Rhodes , Werner Juengling , Thomas A. Figura , Steven D. Cummings
发明人： Howard E. Rhodes , Werner Juengling , Thomas A. Figura , Steven D. Cummings
IPC分类号： H01L2100
CPC分类号： H01L27/14687 , H01L27/14609 , H01L27/14806 , H01L29/8611
摘要： A photodiode for use in an imager having an improved charge leakage. The photodiode has a doped region that is spaced away from the field isolation to minimize charge leakage. A second embodiment of invention provides a second implant to improve charge leakage to the substrate. The photodiodes according to the invention provide improve charge leakage, improved reactions to dark current and an improved signal to noise ratio. Also disclosed are processes for forming the photodiode.
摘要翻译：用于具有改善的电荷泄漏的成像器中的光电二极管。光电二极管具有与场隔离间隔开的掺杂区域，以最小化电荷泄漏。本发明的第二实施例提供了一种第二种植入物，用于改善对衬底的电荷泄漏。根据本发明的光电二极管提供改善电荷泄漏，改善对暗电流的反应和改善的信噪比。还公开了用于形成光电二极管的工艺。

3. 发明授权

US07943505B2 Advanced VLSI metallization 有权
标题翻译：先进的VLSI金属化
公开(公告)号：US07943505B2
公开(公告)日：2011-05-17
申请号：US10871242
申请日：2004-06-18
申请人： Howard E. Rhodes , Steven D. Cummings
发明人： Howard E. Rhodes , Steven D. Cummings
IPC分类号： H01L21/4763
CPC分类号： H01L21/7685 , H01L21/32051 , H01L21/76838 , H01L23/49866 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A four layer interconnect structure is disclosed which includes a bottom conductive reactive layer such as titanium, a conductive barrier layer, such as titanium nitride, a conductive layer, such as aluminum-copper alloy, and a top conductive barrier layer, such as titanium nitride. The interconnection structure can be fabricated using conventional sputter deposition technology. The resulting interconnection structure provides a highly conductive thin film structure that provides good contact to tungsten plugs with small contact dimensions, good patternability on fine lines, and good reliability.
摘要翻译：公开了一种四层互连结构，其包括诸如钛的底部导电反应层，诸如氮化钛的导电阻挡层，诸如铝 - 铜合金的导电层和顶部导电阻挡层，例如氮化钛。可以使用常规的溅射沉积技术来制造互连结构。所得到的互连结构提供了一种高导电性薄膜结构，其对接触尺寸小的钨插头提供良好的接触，在细线上具有良好的可模式性和良好的可靠性。

4. 发明授权

US5371701A Stacked delta cell capacitor 失效
标题翻译：堆叠式三角形电容器
公开(公告)号：US5371701A
公开(公告)日：1994-12-06
申请号：US223477
申请日：1994-04-05
申请人： Ruojia Lee , Charles H. Dennison , Yauh-Ching Liu , Pierre Fazan , Steven D. Cummings
发明人： Ruojia Lee , Charles H. Dennison , Yauh-Ching Liu , Pierre Fazan , Steven D. Cummings
IPC分类号： H01L27/108 , H01L29/68
CPC分类号： H01L27/10817
摘要： A stacked delta cell (SDC) capacitor using a modified stacked capacitor storage cell fabrication process. The SDC is made up of polysilicon structure, having an inverted deltoid cross section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 120% without enlarging the surface area defined for a normal stacked capacitor cell.
摘要翻译：使用改进的堆叠电容器存储单元制造工艺的堆叠三角形电池（SDC）电容器。 SDC由具有倒三角形横截面的多晶硅结构构成，位于掩埋接触处，并延伸到由多晶硅覆盖的相邻存储节点之间，介电夹在其间。多晶硅结构的添加增加了存储能力120％，而不会扩大为正常层叠电容器单元限定的表面积。

5. 发明授权

US06812112B2 Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers 失效
公开(公告)号：US06812112B2
公开(公告)日：2004-11-02
申请号：US09965509
申请日：2001-09-26
申请人： Cem Basceri , Mark Visokay , Thomas M. Graettinger , Steven D. Cummings
发明人： Cem Basceri , Mark Visokay , Thomas M. Graettinger , Steven D. Cummings
IPC分类号： H01L218242
CPC分类号： H01L28/82 , H01L28/55
摘要： An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used. In the case of this etchant and a ruthenium/ruthenium oxide film, the etchant preferentially removes the ruthenium phase, leaving a pitted or “islanded” surface of ruthenium oxide physically and electrically connected by the underlying conductive layer. The remaining pitted or islanded layer, together with the underlying conductive layer, if any, constitutes an enhanced-surface-area conductive layer. The enhanced-surface-area conductive layer may be used to form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like.

6. 发明授权

US5321649A Stacked delta cell capacitor 失效
公开(公告)号：US5321649A
公开(公告)日：1994-06-14
申请号：US76300
申请日：1993-06-11
申请人： Ruojia Lee , Charles H. Dennison , Yauh-Ching Liu , Pierre Fazan , Steven D. Cummings
发明人： Ruojia Lee , Charles H. Dennison , Yauh-Ching Liu , Pierre Fazan , Steven D. Cummings
IPC分类号： H01L27/108 , H01L29/68
CPC分类号： H01L27/10817
摘要： A stacked delta cell (SDC) capacitor using a modified stacked capacitor storage cell fabrication process. The SDC is made up of polysilicon structure, having an inverted deltoid cross section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 120% without enlarging the surface area defined for a normal stacked capacitor cell.

7. 发明授权

US07271413B2 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US07271413B2
公开(公告)日：2007-09-18
申请号：US11274727
申请日：2005-11-14
申请人： Randal W. Chance , Gordon A. Haller , Sanh D. Tang , Steven D. Cummings
发明人： Randal W. Chance , Gordon A. Haller , Sanh D. Tang , Steven D. Cummings
IPC分类号： H01L27/108
CPC分类号： H01L29/66666 , H01L21/823437 , H01L21/823487 , H01L27/10808 , H01L27/10876 , H01L29/42368 , H01L29/512 , H01L29/7827
摘要： The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending pillars can be incorporated into transistor devices, and can contain vertically-extending channel regions of the transistor devices. The transistor devices can be incorporated into integrated circuitry, and in some aspects are incorporated into memory constructions, such as, for example, dynamic random access memory (DRAM) constructions.
摘要翻译：本发明包括包含垂直延伸柱的半导体结构以及用于形成这种结构的方法。垂直延伸的柱可以并入晶体管器件中，并且可以包含晶体管器件的垂直延伸的沟道区域。晶体管器件可以并入到集成电路中，并且在一些方面被并入存储器结构中，例如动态随机存取存储器（DRAM）结构。

8. 发明授权

US07253102B2 Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers 失效
标题翻译：包含增强表面积导电层的形成方法和集成电路结构
公开(公告)号：US07253102B2
公开(公告)日：2007-08-07
申请号：US10860341
申请日：2004-06-02
申请人： Cem Basceri , Mark Visokay , Thomas M. Graettinger , Steven D. Cummings
发明人： Cem Basceri , Mark Visokay , Thomas M. Graettinger , Steven D. Cummings
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L28/82 , H01L28/55
摘要： An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used. In the case of this etchant and a ruthenium/ruthenium oxide film, the etchant preferentially removes the ruthenium phase, leaving a pitted or “islanded” surface of ruthenium oxide physically and electrically connected by the underlying conductive layer. The remaining pitted or islanded layer, together with the underlying conductive layer, if any, constitutes an enhanced-surface-area conductive layer. The enhanced-surface-area conductive layer may be used to form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like.
摘要翻译：与高介电常数材料兼容的增强表面积导电层是通过形成具有至少两个相的膜或层，其中至少一个导电层是导电的。膜可以以任何方便的方式形成，例如通过化学气相沉积技术，其后可以进行退火以更好地限定和/或结晶至少两个相。膜可以形成在下面的导电层上。所述至少两个相中的至少一个相被选择性地从膜上移除，例如通过蚀刻工艺，其优先蚀刻至少两个相中的至少一个，以便留下导电相的至少一部分。导电的钌和氧化钌可以用于两个或多个相。也可以使用铱及其氧化物，铑及其氧化物，以及铂和铂 - 铑。可以使用包含硝酸铈铵和乙酸的湿蚀刻剂。在这种蚀刻剂和钌/氧化钌膜的情况下，蚀刻剂优先除去钌相，留下通过下面的导电层物理和电连接的氧化钌的凹陷或“孤立”的表面。剩余的凹陷或孤岛层与下面的导电层（如果有的话）一起构成增强的表面积导电层。增强表面积导电层可用于在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。

9. 发明授权

US07122425B2 Methods of forming semiconductor constructions 有权
公开(公告)号：US07122425B2
公开(公告)日：2006-10-17
申请号：US10925789
申请日：2004-08-24
申请人： Randal W. Chance , Gordon A. Haller , Sanh D. Tang , Steven D. Cummings
发明人： Randal W. Chance , Gordon A. Haller , Sanh D. Tang , Steven D. Cummings
IPC分类号： H01L21/8242
CPC分类号： H01L29/66666 , H01L21/823437 , H01L21/823487 , H01L27/10808 , H01L27/10876 , H01L29/42368 , H01L29/512 , H01L29/7827
摘要： The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending pillars can be incorporated into transistor devices, and can contain vertically-extending channel regions of the transistor devices. The transistor devices can be incorporated into integrated circuitry, and in some aspects are incorporated into memory constructions, such as, for example, dynamic random access memory (DRAM) constructions.

10. 发明授权

US06764943B2 Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers 失效
标题翻译：包含增强表面积导电层的形成方法和集成电路结构
公开(公告)号：US06764943B2
公开(公告)日：2004-07-20
申请号：US10196535
申请日：2002-07-15
申请人： Cem Basceri , Mark Visokay , Thomas M. Graettinger , Steven D. Cummings
发明人： Cem Basceri , Mark Visokay , Thomas M. Graettinger , Steven D. Cummings
IPC分类号： H01L214763
CPC分类号： H01L28/82 , H01L28/55
摘要： An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used. In the case of this etchant and a ruthenium/ruthenium oxide film, the etchant preferentially removes the ruthenium phase, leaving a pitted or “islanded” surface of ruthenium oxide physically and electrically connected by the underlying conductive layer. The remaining pitted or islanded layer, together with the underlying conductive layer, if any, constitutes an enhanced-surface-area conductive layer. The enhanced-surface-area conductive layer may be used to form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like.
摘要翻译：与高介电常数材料兼容的增强表面积导电层是通过形成具有至少两个相的膜或层，其中至少一个导电层是导电的。膜可以以任何方便的方式形成，例如通过化学气相沉积技术，其后可以进行退火以更好地限定和/或结晶至少两个相。膜可以形成在下面的导电层上。所述至少两个相中的至少一个相被选择性地从膜上移除，例如通过蚀刻工艺，其优先蚀刻至少两个相中的至少一个，以便留下导电相的至少一部分。导电的钌和氧化钌可以用于两个或多个相。也可以使用铱及其氧化物，铑及其氧化物，以及铂和铂 - 铑。可以使用包含硝酸铈铵和乙酸的湿蚀刻剂。在这种蚀刻剂和钌/氧化钌膜的情况下，蚀刻剂优先除去钌相，留下通过下面的导电层物理和电连接的氧化钌的凹陷或“孤立”的表面。剩余的凹陷或孤岛层与下面的导电层（如果有的话）一起构成增强的表面积导电层。增强表面积导电层可用于在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。

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