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1. 发明授权

US6026047A Integrated circuit memory device with hierarchical work line structure 有权
标题翻译：具有分层工作线结构的集成电路存储器件
公开(公告)号：US6026047A
公开(公告)日：2000-02-15
申请号：US185090
申请日：1998-11-03
申请人： Hoon Ryu , Jun-Young Jeon
发明人： Hoon Ryu , Jun-Young Jeon
IPC分类号： G11C11/407 , G11C8/08 , G11C8/10 , G11C8/14 , G11C8/00
CPC分类号： G11C8/14 , G11C8/08 , G11C8/10
摘要： A dynamic random access memory device includes sub-word line drivers to drive sub-word lines up to a boosted voltage level. Each sub-word line driver generates a sub-word drive signal to drive a corresponding sub-word line in response to main-word decode signal and a sub-word decode signal. Each of the sub-word line drivers includes an N-channel MOS pull-up transistor and an N-channel MOS precharge transistor whose threshold voltages are different from each other. The conduction path of the pull-up transistor is coupled between the sub-word decode signal and the corresponding sub-word line. The precharge transistor has a conduction path coupled between the main-word line and the control electrode of the pull-up transistor. The control electrode of the precharge transistor is coupled to the boosted voltage. The boosted voltage is larger than the power supply voltage by twice the threshold voltage of the pull-up transistor. The threshold voltage of the precharge transistor is smaller than that of the pull-up transistor.
摘要翻译：动态随机存取存储器件包括用于驱动子字线直到提升的电压电平的子字线驱动器。每个子字线驱动器响应于主字解码信号和子字解码信号产生子字驱动信号以驱动对应的子字线。每个子字线驱动器包括N沟道MOS上拉晶体管和阈值电压彼此不同的N沟道MOS预充电晶体管。上拉晶体管的导通路径耦合在子字解码信号和对应的子字线之间。预充电晶体管具有耦合在主字线和上拉晶体管的控制电极之间的导通路径。预充电晶体管的控制电极耦合到升压电压。升压电压大于电源电压的两倍于上拉晶体管的阈值电压。预充电晶体管的阈值电压小于上拉晶体管的阈值电压。

2. 发明授权

US06212121B1 Semiconductor memory device with multiple sub-arrays of different sizes 有权
标题翻译：具有不同尺寸的多个子阵列的半导体存储器件
公开(公告)号：US06212121B1
公开(公告)日：2001-04-03
申请号：US09451466
申请日：1999-11-30
申请人： Hoon Ryu , Moon-Chan Hwang , Jun-Young Jeon
发明人： Hoon Ryu , Moon-Chan Hwang , Jun-Young Jeon
IPC分类号： G11C800
CPC分类号： G11C8/12
摘要： A semiconductor memory device includes a memory cell array divided into a plurality of sub-arrays. The number of memory cells per bit line in at least one of the sub-arrays differs from the number of memory cells per bit line in other sub-arrays. When the sense amplifiers can accommodate a bit line loading of (2M+2M/N) memory cells per bit line, the size and bit line loading of one of more of the sub-arrays can be increased. This can provide sub-arrays of different sizes and can reduce the number of the sub-arrays and the number of the sense amplifier regions. Accordingly, the chip efficiency is improved. Maximum current for sensing during simultaneous accesses of multiple arrays can access two sub-arrays with different bit line loadings and avoid simultaneously accessing two sub-arrays having high bit-line loadings.
摘要翻译：半导体存储器件包括分成多个子阵列的存储单元阵列。至少一个子阵列中每位线的存储单元的数量与其他子阵列中每位线的存储单元的数量不同。当读出放大器可以容纳每个位线的（2M + 2M / N）个存储单元的位线负载时，可以增加更多子阵列之一的大小和位线负载。这可以提供不同尺寸的子阵列，并且可以减少子阵列的数量和读出放大器区域的数量。因此，提高了芯片效率。在同时访问多个阵列期间感测的最大电流可以访问具有不同位线负载的两个子阵列，并避免同时访问具有高位线负载的两个子阵列。

3. 发明授权

US6147924A Arrangement of data input/output circuits for use in a semiconductor memory device 有权
标题翻译：用于半导体存储器件中的数据输入/输出电路的布置
公开(公告)号：US6147924A
公开(公告)日：2000-11-14
申请号：US330264
申请日：1999-06-11
申请人： Chang-Ho Lee , Jun-Young Jeon
发明人： Chang-Ho Lee , Jun-Young Jeon
IPC分类号： H01L27/10 , G11C5/02 , G11C8/00
CPC分类号： G11C5/025
摘要： There is provided a semiconductor memory device which includes a plurality of memory cell blocks arranged in rows and columns. Each memory cell block includes a plurality of memory cells for storing data. A plurality of data input/output circuits are divided into a first group and a second group. The first group and the second group are associated with and disposed between a respective subset of the memory cell blocks. The data input/output circuits have a plurality of data input/output pins. A plurality of address signal circuits are arranged between the first group and the second group for receiving externally applied address signals. The semiconductor memory device is packed using a Non-Outer-DQ-Inner-Control (NON-ODIC) type package having a structure such that the data input/output pins of the data input/output circuits of the first and second groups are collectively arranged adjacent to each other.
摘要翻译：提供了一种半导体存储器件，其包括以行和列排列的多个存储单元块。每个存储单元块包括用于存储数据的多个存储单元。多个数据输入/输出电路被分成第一组和第二组。第一组和第二组与存储单元块的相应子集相关联并且被布置在存储单元块的相应子集之间。数据输入/输出电路具有多个数据输入/输出引脚。多个地址信号电路被布置在第一组和第二组之间用于接收外部施加的地址信号。半导体存储器件使用非外部DQ-内部控制（NON-ODIC）型封装进行封装，该封装具有使得第一和第二组的数据输入/输出电路的数据输入/输出引脚集体的结构彼此相邻布置。

4. 发明授权

US5701072A Integrated circuit output driver systems including multiple power and ground lines 失效
标题翻译：集成电路输出驱动器系统，包括多个电源和地线
公开(公告)号：US5701072A
公开(公告)日：1997-12-23
申请号：US702130
申请日：1996-08-23
申请人： Jun-Young Jeon , Pil-Soon Park
发明人： Jun-Young Jeon , Pil-Soon Park
IPC分类号： G11C11/417 , G05F3/24 , G11C11/401 , G11C11/409 , H03K19/00 , H03K19/0175 , G05F3/04 , H01H3/26
CPC分类号： G05F3/242
摘要： An integrated circuit output driver system includes a first power line channel extending along the integrated circuit. The first power line channel includes a first power supply voltage line and a first ground voltage line. A second power line channel also extends along the integrated circuit and is spaced apart from the first power line channel. The second power line channel includes a second power supply voltage line and a second ground voltage line. A plurality of output drivers are located between the first and second spaced apart power line channels. Each output driver includes an output node, a pull-up circuit which pulls up the output node in response to a pull-up input signal, and a pull-down circuit which pulls down the output node in response to a pull-down input signal. The power supply and ground voltage connections for alternating output drivers are supplied by the first power supply voltage line and the second ground voltage line, and the second power supply voltage line and the first ground voltage line respectively. Switching noise on the power lines may thereby be reduced.
摘要翻译：集成电路输出驱动器系统包括沿集成电路延伸的第一电力线通道。第一电力线通道包括第一电源电压线和第一接地电压线。第二电力线通道也沿着集成电路延伸并且与第一电力线通道间隔开。第二电力线通道包括第二电源电压线和第二接地电压线。多个输出驱动器位于第一和第二间隔开的电力线通道之间。每个输出驱动器包括输出节点，上拉电路，其响应于上拉输入信号上拉输出节点;以及下拉电路，其响应于下拉输入信号而拉下输出节点。交流输出驱动器的电源和地电压连接分别由第一电源电压线和第二接地电压线，第二电源电压线和第一接地电压线提供。因此可以减少电力线上的开关噪声。

5. 发明授权

US6094382A Integrated circuit memory devices with improved layout of fuse boxes and buses 有权
标题翻译：集成电路存储器件，具有改进的保险丝盒和总线布局
公开(公告)号：US6094382A
公开(公告)日：2000-07-25
申请号：US200008
申请日：1998-11-25
申请人： Jong-Hyun Choi , Jun-Young Jeon
发明人： Jong-Hyun Choi , Jun-Young Jeon
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C29/80
摘要： A row redundancy fuse box that replaces a defective row with a redundant row of an integrated circuit memory device is located between a row decoder, a row predecoder and a subarray block control circuit. By locating the row redundancy fuse box between the row decoder and the subarray block control circuit, the size of an integrated circuit memory device and the bus line loading in the device may be reduced. A row predecoder is coupled to the row redundancy fuse box and is located remote from the row decoder, the subarray block control circuit and the row redundancy fuse box. A column decoder is located adjacent the row predecoder and remote from the row decoder, the subarray block control circuit and the row redundancy fuse box. A pad layer receives and transmits external input and output signals respectively, and is located adjacent the subarray block control circuit, opposite the row redundancy fuse box. The predecoded row address bus and the row decoder overlap one another in the integrated circuit memory device. More specifically, the row decoder is preferably beneath the predecoded row address bus in the integrated circuit memory device. This can also decrease the size of the integrated circuit memory device. According to another aspect, the redundancy enable bus extends from the fuse box, up to but not beyond the predecoded row address bus.
摘要翻译：行冗余保险丝盒用于替代具有集成电路存储器件的冗余行的有缺陷的行位于行解码器，行预解码器和子阵列块控制电路之间。通过将行冗余保险丝盒定位在行解码器和子阵列块控制电路之间，可以减小集成电路存储器件的尺寸和装载中的总线线路。一行预解码器耦合到行冗余保险丝盒，并且位于远离行解码器，子阵列控制电路和行冗余保险丝盒的位置。列解码器位于行预解码器附近并且远离行解码器，子阵列控制电路和行冗余保险丝盒。衬垫层分别接收和发送外部输入和输出信号，并且位于与阵列冗余保险丝盒相对的子阵列控制电路附近。预解码行地址总线和行解码器在集成电路存储器件中彼此重叠。更具体地，行解码器优选地在集成电路存储器件中的预编码行地址总线下方。这也可以减小集成电路存储器件的尺寸。根据另一方面，冗余使能总线从保险丝盒延伸到但不超过预先解码的行地址总线。

6. 发明授权

US5930166A Semiconductor memory device with triple metal layer 失效
标题翻译：具有三重金属层的半导体存储器件
公开(公告)号：US5930166A
公开(公告)日：1999-07-27
申请号：US986905
申请日：1997-12-08
申请人： Jun-Young Jeon
发明人： Jun-Young Jeon
IPC分类号： G11C11/41 , G11C5/02 , G11C11/401 , H01L21/28 , H01L21/3205 , H01L21/82 , H01L21/8242 , H01L23/52 , H01L23/528 , H01L27/108 , G11C11/34
CPC分类号： H01L23/5286 , G11C5/025 , H01L2924/0002
摘要： A semiconductor memory device formed using a triple metal process to minimize the chip area required to define such a circuit. The semiconductor memory device having a memory cell array and a peripheral circuit for reading and writing data from and into a memory cell. The peripheral circuit includes a circuit layer, a first servicing circuit, a second servicing circuit and a third servicing circuit. The circuit layer, such as a decoder or buffer, defines a peripheral circuit layer area of a semiconductor chip. The first servicing circuit, preferably input/output lines, is defined vertically relative to said peripheral circuit layer area in a first metal layer located in said semiconductor chip. The second servicing circuit, preferably signal bussing lines, is defined vertically relative to said first servicing circuit in a second metal layer located in said semiconductor chip. Finally, the third servicing circuit, such as a power line layer, is defined in a third meal layer vertically relative to said second servicing circuit.
摘要翻译：一种使用三重金属工艺形成的半导体存储器件，以最小化限定这种电路所需的芯片面积。具有存储单元阵列的半导体存储器件和用于从存储单元读取和写入数据的外围电路。外围电路包括电路层，第一维修电路，第二维修电路和第三维修电路。诸如解码器或缓冲器的电路层限定半导体芯片的外围电路层区域。第一维修电路，优选输入/输出线，相对于位于所述半导体芯片中的第一金属层中的所述外围电路层区域垂直地定义。在位于所述半导体芯片中的第二金属层中，相对于所述第一维修电路垂直地限定第二维修电路，即信号总线。最后，第三维修电路，例如电力线层，被定义在垂直于第二维修电路的第三餐层中。

7. 发明授权

US5747974A Internal supply voltage generating circuit for semiconductor memory device 失效
标题翻译：用于半导体存储器件的内部电源电压发生电路
公开(公告)号：US5747974A
公开(公告)日：1998-05-05
申请号：US664952
申请日：1996-06-12
申请人： Jun-Young Jeon
发明人： Jun-Young Jeon
IPC分类号： G11C11/407 , G05F1/46 , G11C5/14 , G11C11/401 , G05F1/59
CPC分类号： G05F1/465
摘要： Internal supply voltage generating circuits generate internal supply voltages at voltage levels below an external supply voltage. The internal supply voltages operate peripheral circuits and array circuits. A reference voltage generates a constant reference voltage. First and second dividing circuits output a given voltage in response to the internal supply voltage. First and second differential amplifiers compare the reference voltage with each of the output voltages from the first and second dividing circuits. First and second driving circuits supply the internal supply voltage from the external supply voltage. First and second voltage boosting circuits clamp output voltage levels for the first and second driving circuits from the external supply voltage and raise the clamped output voltage level of the first driving circuit higher than the clamped output voltage level of the second driving circuit. The boosting circuits maintain a voltage offset between the first and second internal voltage supplies when the external supply voltage is increased above a normal operating range.
摘要翻译：内部电源电压产生电路在低于外部电源电压的电压电平下产生内部电源电压。内部电源电压操作外围电路和阵列电路。参考电压产生恒定的参考电压。第一和第二分频电路响应于内部电源电压输出给定的电压。第一和第二差分放大器将参考电压与来自第一和第二分频电路的每个输出电压进行比较。第一和第二驱动电路从外部电源电压提供内部电源电压。第一和第二升压电路将来自外部电源电压的第一和第二驱动电路的输出电压电平钳位，并将第一驱动电路的钳位输出电压电平提高到高于第二驱动电路的钳位输出电压电平。当外部电源电压增加到正常工作范围以上时，升压电路保持第一和第二内部电源之间的电压偏移。

8. 发明授权

US5455192A Method of making dynamic random access memory cell having a stacked capacitor and a trench capacitor 失效
标题翻译：制造具有堆叠电容器和沟槽电容器的动态随机存取存储器单元的方法
公开(公告)号：US5455192A
公开(公告)日：1995-10-03
申请号：US719341
申请日：1991-06-24
申请人： Jun-Young Jeon
发明人： Jun-Young Jeon
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/1085 , H01L27/10835
摘要： A method of making a DRAM cell capable of increasing storage capacity and for which is amenable to large-scale integration. The method provides a DRAM cell having stacked and trench capacitors and a transistor of second conductivity type opposite to a first conductivity type on a semiconductor substrate of the first conductivity type. Polycrystalline silicon of a cell node in the stack capacitor is coupled to source region of the transistor. Cell node of the trench capacitor is coupled to the source region of transistor through N-type diffusion region around the trench that is formed between said source region and a field oxide. Over the trench capacitor is disposed the stack capacitor, and the cell nodes are coupled to each other. A cell plate filling the inside of the trench may be used in common since it surrounds the polycrystalline silicon, that is, the cell node of stack capacitor.
摘要翻译：制造能够增加存储容量并且适合于大规模集成的DRAM单元的方法。该方法提供具有层叠和沟槽电容器的DRAM单元和在第一导电类型的半导体衬底上与第一导电类型相反的第二导电类型的晶体管。堆叠电容器中的单元节点的多晶硅耦合到晶体管的源极区域。沟槽电容器的单元节点通过形成在所述源极区域和场氧化物之间的沟槽周围的N型扩散区域耦合到晶体管的源极区域。在沟槽电容器上设置堆叠电容器，并且单元节点彼此耦合。填充沟槽内部的电池板可以共同使用，因为它围绕多晶硅，即堆叠电容器的电池节点。

9. 发明授权

US5027172A Dynamic random access memory cell and method of making thereof 失效
标题翻译：动态随机存取存储单元及其制造方法
公开(公告)号：US5027172A
公开(公告)日：1991-06-25
申请号：US451775
申请日：1989-12-18
申请人： Jun-Young Jeon
发明人： Jun-Young Jeon
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1085 , H01L27/10835
摘要： A method of making a DRAM cell capable of increaisng storage capacity and for which is amendable to large-scale integration. The method provides a DRAM cell having stacked and trench capacitors and a transistor of second conductivity type opposite to a first conductivity type on a semiconductor substrate of the first conductivity type. Polycrystalline silicon of a cell node in the stack capacitor is coupled to source region of the transistor. The cell node of the trench capacitor is coupled to the source region of the transistor through an N-type diffusion region around the trench that is formed between said source region and a field oxide. Over the trench capacitor is disposed the stacked capacitor, and the cell nodes are coupled to each other. A cell plate filling the inside of the trench may be used in common since it surrounds the polycrystalline silicon, that is, the cell node of the stacked capacitor.
摘要翻译：制造能够增加存储容量的DRAM单元的方法，其可修改为大规模集成。该方法提供具有层叠和沟槽电容器的DRAM单元和在第一导电类型的半导体衬底上与第一导电类型相反的第二导电类型的晶体管。堆叠电容器中的单元节点的多晶硅耦合到晶体管的源极区域。沟槽电容器的单元节点通过形成在所述源极区域和场氧化物之间的沟槽周围的N型扩散区域耦合到晶体管的源极区域。在沟槽电容器上设置堆叠的电容器，并且单元节点彼此耦合。填充沟槽内部的电池板可以共同使用，因为它围绕多晶硅，即堆叠电容器的电池节点。

10. 发明授权

US06274931B1 Integrated circuit packaging systems and methods that use the same packaging substrates for integrated circuits of different data path widths 有权
标题翻译：集成电路封装系统和方法，使用不同数据路径宽度的集成电路的相同封装基板
公开(公告)号：US06274931B1
公开(公告)日：2001-08-14
申请号：US09395649
申请日：1999-09-14
申请人： Jun-Young Jeon , Jong-Hyun Choi
发明人： Jun-Young Jeon , Jong-Hyun Choi
IPC分类号： H01L2348
CPC分类号： H01L23/49838 , H01L21/485 , H01L23/50 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit packages include an integrated circuit substrate having microelectronic devices therein and pads, wherein first ones of the pads are enabled to provide output data from the microelectronic devices, and wherein second ones of the pads are disabled to provide a reduced path width for the integrated circuit substrate. A packaging substrate includes terminals, a respective one of which is connected to a respective one of the pads, including the second ones of pads that are disabled to provide a reduced path width for the integrated circuit substrate. Accordingly, the same packaging substrates may be used with integrated circuit substrates having different path widths. In a preferred embodiment, the integrated circuit substrate includes a control circuit that disables the second ones of the pads to provide a reduced path width for the integrated circuit substrate. The control circuit preferably includes at least one fuse that disables the second ones of pads to provide the reduced path width for the integrated circuit substrate.
摘要翻译：集成电路封装包括其中具有微电子器件的集成电路衬底和焊盘，其中第一焊盘能够提供来自微电子器件的输出数据，并且其中第二焊盘被禁用以提供集成的减小的路径宽度电路基板。封装基板包括端子，其中的一个连接到相应的一个焊盘，包括禁用以提供集成电路基板的减小的路径宽度的第二焊盘。因此，相同的封装基板可以与具有不同路径宽度的集成电路基板一起使用。在优选实施例中，集成电路基板包括禁止第二个焊盘以提供集成电路基板的减小路径宽度的控制电路。控制电路优选地包括至少一个保险丝，其禁用第二个焊盘以为集成电路基板提供减小的路径宽度。

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