专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07332973B2 Circuit and method for digital phase-frequency error detection 失效
标题翻译：数字相位频率误差检测电路及方法
公开(公告)号：US07332973B2
公开(公告)日：2008-02-19
申请号：US11265442
申请日：2005-11-02
申请人： Hoon Lee , Tirdad Sowlati
发明人： Hoon Lee , Tirdad Sowlati
IPC分类号： H03L7/089 , H03L7/097
CPC分类号： G04F10/005 , H03L7/085 , H03L7/091
摘要： A time-to-digital converter comprises a ring oscillator, a counter, an encoder, and a multi-bit latch. The ring oscillator comprises a first input and a clock input, as well as, a first output responsive to a single cycle of the ring oscillator and a second output responsive to a signal applied at the first input. A counter coupled to the first output generates a first binary word. An encoder coupled to the second output generates a second binary word. The multi-bit latch receives the first and second binary words and generates a composite representation of a phase-frequency error signal. The time-to-digital converter is well suited for digital phase-locked loops used in communications applications and digital phase-locked loops in electromechanical control systems that require high-precision phase-frequency error detection.
摘要翻译：时间 - 数字转换器包括环形振荡器，计数器，编码器和多位锁存器。环形振荡器包括第一输入和时钟输入，以及响应于环形振荡器的单个周期的第一输出和响应于在第一输入处施加的信号的第二输出。耦合到第一输出的计数器产生第一个二进制字。耦合到第二输出的编码器产生第二二进制字。多位锁存器接收第一和第二二进制字，并产生相位 - 频率误差信号的复合表示。时间到数字转换器非常适用于需要高精度相位频率误差检测的机电控制系统中通信应用和数字锁相环中使用的数字锁相环。

2. 发明申请

US20070096836A1 Circuit and method for digital phase-frequency error detection 失效
标题翻译：数字相位频率误差检测电路及方法
公开(公告)号：US20070096836A1
公开(公告)日：2007-05-03
申请号：US11265442
申请日：2005-11-02
申请人： Hoon Lee , Tirdad Sowlati
发明人： Hoon Lee , Tirdad Sowlati
IPC分类号： H03K3/03
CPC分类号： G04F10/005 , H03L7/085 , H03L7/091
摘要： A time-to-digital converter comprises a ring oscillator, a counter, an encoder, and a multi-bit latch. The ring oscillator comprises a first input and a clock input, as well as, a first output responsive to a single cycle of the ring oscillator and a second output responsive to a signal applied at the first input. A counter coupled to the first output generates a first binary word. An encoder coupled to the second output generates a second binary word. The multi-bit latch receives the first and second binary words and generates a composite representation of a phase-frequency error signal. The time-to-digital converter is well suited for digital phase-locked loops used in communications applications and digital phase-locked loops in electromechanical control systems that require high-precision phase-frequency error detection.
摘要翻译：时间 - 数字转换器包括环形振荡器，计数器，编码器和多位锁存器。环形振荡器包括第一输入和时钟输入，以及响应于环形振荡器的单个周期的第一输出和响应于在第一输入处施加的信号的第二输出。耦合到第一输出的计数器产生第一个二进制字。耦合到第二输出的编码器产生第二二进制字。多位锁存器接收第一和第二二进制字，并产生相位 - 频率误差信号的复合表示。时间到数字转换器非常适用于需要高精度相位频率误差检测的机电控制系统中通信应用和数字锁相环中使用的数字锁相环。

3. 发明授权

US09000572B2 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US09000572B2
公开(公告)日：2015-04-07
申请号：US13567394
申请日：2012-08-06
申请人： Hoon Lee , Sang-Bo Lee
发明人： Hoon Lee , Sang-Bo Lee
IPC分类号： H01L23/02 , H01L21/00 , H01L23/48 , H01L23/00 , H01L25/065 , H01L23/31
CPC分类号： H01L23/481 , H01L23/3128 , H01L24/13 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2224/131 , H01L2224/16146 , H01L2224/16225 , H01L2224/17135 , H01L2224/17136 , H01L2224/17517 , H01L2924/181 , H01L2924/3511 , H01L2924/014 , H01L2924/00
摘要： A semiconductor package substrate may include a first semiconductor chip, a second semiconductor chip, plugs and interconnection terminals. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The first and second semiconductor chips may have corresponding first regions and corresponding second regions. Conductive plugs may be built only in a first region of the first semiconductor chip. Circuitry of the second semiconductor chip may only be electrically connected to the first semiconductor chip through the conductive connectors corresponding to the first regions of the first and second semiconductor chips.
摘要翻译：半导体封装基板可以包括第一半导体芯片，第二半导体芯片，插头和互连端子。第二半导体芯片可以布置在第一半导体芯片的上表面上。第一和第二半导体芯片可以具有对应的第一区域和对应的第二区域。导电插头可以仅构建在第一半导体芯片的第一区域中。第二半导体芯片的电路只能通过对应于第一和第二半导体芯片的第一区域的导电连接器与第一半导体芯片电连接。

4. 发明授权

US08976713B2 Method and apparatus for performing transmission and reception simultaneously in same frequency band 有权
标题翻译：用于在相同频带中同时进行发送和接收的方法和装置
公开(公告)号：US08976713B2
公开(公告)日：2015-03-10
申请号：US13564367
申请日：2012-08-01
申请人： Seungjae Bahng , Hoon Lee
发明人： Seungjae Bahng , Hoon Lee
IPC分类号： H01Q21/06 , H01Q3/00 , H04B7/02 , H04L27/00 , H04B1/38 , H04M1/00 , H04B7/10 , H04L27/233 , H01Q3/08
CPC分类号： H04B7/10 , H01Q3/08 , H04L27/2332
摘要： There are provided a method and apparatus for transmitting and receiving signals in the same frequency band at the same time. A signal is received using a dual polarization antenna, the main axis of the polarization of the reception signal is predicted by performing adaptive polarization tracking, and polarization filtering is performed in order to remove interference. A signal is transmitted through a polarization completely orthogonal to the tracked polarization. In accordance with the present invention, in a wireless communication system, signals can be transmitted and received in the same frequency band at the same time.
摘要翻译：提供了一种在同一频带内发送和接收信号的方法和装置。使用双极化天线接收信号，通过执行自适应偏振跟踪来预测接收信号的极化的主轴，并执行偏振滤波以消除干扰。通过与跟踪的极化完全正交的偏振来传输信号。根据本发明，在无线通信系统中，可以同时在相同频带中发送和接收信号。

5. 发明授权

US08552569B2 Stacked semiconductor device including ESD protection circuits and method of fabricating the stacked semiconductor device 有权
标题翻译：包括ESD保护电路的叠层半导体器件和制造叠层半导体器件的方法
公开(公告)号：US08552569B2
公开(公告)日：2013-10-08
申请号：US13517888
申请日：2012-06-14
申请人： Hoon Lee
发明人： Hoon Lee
IPC分类号： H01L29/66
CPC分类号： H01L23/5252 , H01L23/481 , H01L23/5256 , H01L23/62 , H01L24/16 , H01L25/0657 , H01L25/18 , H01L2224/13009 , H01L2224/16146 , H01L2224/16237 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06544 , H01L2225/06565 , H01L2924/12042 , H01L2924/00
摘要： A stacked semiconductor device includes a first semiconductor die that has a front side electrically coupled to a substrate pad, the substrate pad is connected to an exterior, a backside of the first semiconductor die, a first integrated circuit, first ESDs, and TSVs, and the TSVs are coupled to the first integrated circuit and the first ESDs. A second semiconductor die is stacked above the backside of the first semiconductor die, the second semiconductor die includes a second integrated circuit that is electrically connected to the TSVs and second ESDs, and the second ESDs is electrically disconnected from the TSVs. The TSVs penetrate the first semiconductor die and extend to the backside of the first semiconductor die.
摘要翻译：叠层半导体器件包括第一半导体管芯，其具有电耦合到衬底焊盘的前侧，衬底焊盘连接到外部，第一半导体管芯的背面，第一集成电路，第一ESD和TSV，以及 TSV耦合到第一集成电路和第一ESD。第二半导体管芯堆叠在第一半导体管芯的背面之上，第二半导体管芯包括与TSV和第二ESD电连接的第二集成电路，并且第二ESD与TSV电断开。 TSV穿透第一半导体管芯并延伸到第一半导体管芯的背面。

6. 发明授权

US08452499B2 System for allocating transmission clutch wear 有权
标题翻译：传动离合器磨损分配系统
公开(公告)号：US08452499B2
公开(公告)日：2013-05-28
申请号：US13218130
申请日：2011-08-25
申请人： Timothy Lorentz , Mathew Guldan , Hoon Lee
发明人： Timothy Lorentz , Mathew Guldan , Hoon Lee
IPC分类号： G06F7/00 , G06F17/00 , G06F19/00
CPC分类号： F16H61/0248 , F16H61/0059 , F16H2059/088 , Y10T477/70 , Y10T477/78
摘要： A control system for a transmission engages three clutches to create braking within the transmission to slow a machine during a shuttle shifting operation. The control system may apply the clutches so as to allocate wear between the clutches equally or unequally, as desired.
摘要翻译：用于变速器的控制系统接合三个离合器以在变速器内产生制动以在换档操作期间减慢机器。控制系统可以应用离合器，以便根据需要在离合器之间分配或不平等地分配磨损。

7. 发明申请

US20110310649A1 Stacked Memory Module and System 有权
标题翻译：堆叠内存模块和系统
公开(公告)号：US20110310649A1
公开(公告)日：2011-12-22
申请号：US13218646
申请日：2011-08-26
申请人： Uk-song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
发明人： Uk-song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/025 , G11C5/04 , G11C8/12 , G11C8/18 , G11C29/14 , H01L23/481 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.
摘要翻译：三维存储器模块和系统形成有在主芯片上堆叠的至少一个从芯片。通过半导体通孔（TSV）通过主芯片和从芯片中的至少一个形成。主芯片包括用于增加存储器模块/系统容量的存储器核心。此外，公开了形成有效布线的三维存储器模块/系统的容量组织，用于形成三维存储器模块/系统的多个存储器组，多个存储体组和/或多个等级。

8. 发明授权

US07751410B2 Apparatus and method for managing traffic using VID in EPON 失效
标题翻译： EPON中使用VID管理流量的装置和方法
公开(公告)号：US07751410B2
公开(公告)日：2010-07-06
申请号：US11635774
申请日：2006-12-07
申请人： Hoon Lee , Tae Whan Yoo , Jung Hak Kim , Yool Kwon , Bong Tae Kim
发明人： Hoon Lee , Tae Whan Yoo , Jung Hak Kim , Yool Kwon , Bong Tae Kim
IPC分类号： H04L12/46
CPC分类号： H04L47/10 , H04L12/4645 , H04L12/66 , H04L47/20 , H04L61/103 , H04L61/6022
摘要： An apparatus and method for managing traffic using a VID in EPON are provided. The apparatus includes a MAC lookup table, a service classification policy table, a service control policy table, a MAC lookup unit, a first and second classification module, a VID learning unit and a first and second service control module. The apparatus classifies all packets of up/downlink transmission flow using a VID into a VID unit, through the first and second classification modules and manages traffic thereof according to the parameters thereof through the first and second service control modules. Accordingly, a large amount of traffic for numerous subscribers and services thereof, which was cannot be processed by the limitation on embodying a typical switch or router, can be processed according to the present invention.
摘要翻译：提供了一种用于使用EPON中的VID来管理业务的装置和方法。该装置包括MAC查找表，服务分类策略表，服务控制策略表，MAC查找单元，第一和第二分类模块，VID学习单元和第一和第二服务控制模块。该装置通过第一和第二分类模块，使用VID将上行/下行链路传输流的所有数据包分类为VID单元，并通过第一和第二服务控制模块根据其参数来管理其流量。因此，根据本发明，可以处理不能通过实施典型交换机或路由器的限制来处理大量用户和其服务的大量业务。

9. 发明申请

US20100154455A1 Dehumidifying Cooling Device for District Heating 审中-公开
标题翻译：用于区域供热的除湿冷却装置
公开(公告)号：US20100154455A1
公开(公告)日：2010-06-24
申请号：US11990087
申请日：2007-03-08
申请人： Seok-Mann Yoon , Dae-Young Lee , Hoon Lee , Chang-Ku Kang , Sung-Ook Jeong
发明人： Seok-Mann Yoon , Dae-Young Lee , Hoon Lee , Chang-Ku Kang , Sung-Ook Jeong
IPC分类号： F25B15/00 , F23L15/02 , F28D15/00
CPC分类号： F24F3/1423 , F24F2203/1024 , F24F2203/1028 , F24F2203/1032 , F24F2203/104 , F24F2203/1072 , F24F2203/1084
摘要： Disclosed is a dehumidifying cooling device for district heating which comprises; a case having a first partition to divide the interior of the case into a wet channel and a dry channel and a second partition to divided the wet channel into a first wet channel and a second wet channel, a sensible heat exchanger to heat exchange the outside air in the first wet channel with the outside air in the second wet channel, a heating coil for raising the temperature of the outside air in the second wet channel, a rotatable de humidifying wheel for adsorbing and removing moisture contained in the circulated air within the dry channel, and a regenerative-evaporative cooler for cooling the circulated air in the dry channel. With this configuration, the device can carry out an air cooling operation by use of hot water supplied by district heating systems and gas or oil boilers installed in individual households, thereby achieving a reduced device size via the implementation of the cooling operation under the atmospheric pressure state and reducing manufacturing costs by virtue of a simplified system configuration.
摘要翻译：公开了一种用于区域供热的除湿冷却装置，包括：壳体具有将壳体内部分成湿通道的第一隔板和干燥通道以及将湿通道分成第一湿通道和第二湿通道的第二隔板，显热交换器以热交换外部第一湿通道中的空气与第二湿通道中的外部空气连通，用于升高第二湿通道中的外部空气的温度的加热线圈，用于吸收和去除包含在第二湿通道内的循环空气中的水分的可旋转脱湿轮干通道和用于冷却干燥通道中的循环空气的再生蒸发冷却器。通过这样的结构，能够通过使用由各个家庭中安装的区域供暖系统和燃气或油锅炉供给的热水进行制冷运转，通过在大气压下实施冷却运转来实现装置尺寸的缩小凭借简化的系统配置降低制造成本。

10. 发明申请

US20100001379A1 Multi-chip package (MCP) having three dimensional mesh-based power distribution network, and power distribution method of the MCP 审中-公开
标题翻译：具有三维网状配电网络的多芯片封装（MCP）以及MCP的功率分配方法
公开(公告)号：US20100001379A1
公开(公告)日：2010-01-07
申请号：US12458124
申请日：2009-07-01
申请人： Hoon Lee , Kang-wook Lee , Uk-song Kang
发明人： Hoon Lee , Kang-wook Lee , Uk-song Kang
IPC分类号： H01L29/40 , H01L21/00 , H01L21/44
CPC分类号： H01L23/5286 , H01L23/481 , H01L25/0657 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A MCP includes a plurality of semiconductor memory devices, the plurality of semiconductor memory devices being stacked to define a three-dimensional (3D) structure, and a mesh structure, the mesh structure interconnecting the plurality of semiconductor memory devices to define a 3D mesh-based power distribution network.
摘要翻译： MCP包括多个半导体存储器件，所述多个半导体存储器件被堆叠以限定三维（3D）结构，以及网格结构，所述网格结构互连所述多个半导体存储器件以限定3D网状结构，基于配电网络。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式