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1. 发明申请

US20060292787A1 Semiconductor processing methods, and semiconductor constructions 有权
标题翻译：半导体加工方法和半导体结构
公开(公告)号：US20060292787A1
公开(公告)日：2006-12-28
申请号：US11168861
申请日：2005-06-28
申请人： Hongmei Wang , Fred Fishburn , Janos Fucsko , T. Allen , Richard Lane , Robert Hanson , Kevin Shea
发明人： Hongmei Wang , Fred Fishburn , Janos Fucsko , T. Allen , Richard Lane , Robert Hanson , Kevin Shea
IPC分类号： H01L21/8244 , H01L29/94
CPC分类号： H01L21/76232
摘要： The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the opening can be protected with a liner while a lower periphery is unlined. The unlined portion can then be etched to form a widened region of the opening. Subsequently, the opening can be filled with insulative material to form an isolation region. Transistor devices can then be formed on opposing sides of the isolation region, and electrically isolated from one another with the isolation region. The invention also includes semiconductor constructions containing an electrically insulative isolation structure extending into a semiconductor material, with the structure having a bulbous bottom region and a stem region extending upwardly from the bottom region to a surface of the semiconductor material.
摘要翻译：本发明包括形成隔离区域的方法。可以形成开口以延伸到半导体材料中，并且可以用衬垫保护开口的上周边，而下边缘是无衬里的。然后可以对无衬里部分进行蚀刻以形成开口的加宽区域。随后，开口可以用绝缘材料填充以形成隔离区域。晶体管器件然后可以形成在隔离区域的相对侧上，并且与隔离区域彼此电隔离。本发明还包括包含延伸到半导体材料中的电绝缘隔离结构的半导体结构，其结构具有球形底部区域和从底部区域向上延伸到半导体材料表面的杆区域。

2. 发明申请

US20070117347A1 Semiconductor constructions 审中-公开
标题翻译：半导体结构
公开(公告)号：US20070117347A1
公开(公告)日：2007-05-24
申请号：US11655386
申请日：2007-01-17
申请人： Hongmei Wang , Fred Fishburn , Janos Fucsko , T. Allen , Richard Lane , Robert Hanson , Kevin Shea
发明人： Hongmei Wang , Fred Fishburn , Janos Fucsko , T. Allen , Richard Lane , Robert Hanson , Kevin Shea
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the opening can be protected with a liner while a lower periphery is unlined. The unlined portion can then be etched to form a widened region of the opening. Subsequently, the opening can be filled with insulative material to form an isolation region. Transistor devices can then be formed on opposing sides of the isolation region, and electrically isolated from one another with the isolation region. The invention also includes semiconductor constructions containing an electrically insulative isolation structure extending into a semiconductor material, with the structure having a bulbous bottom region and a stem region extending upwardly from the bottom region to a surface of the semiconductor material.
摘要翻译：本发明包括形成隔离区域的方法。可以形成开口以延伸到半导体材料中，并且可以用衬垫保护开口的上周边，而下边缘是无衬里的。然后可以对无衬里部分进行蚀刻以形成开口的加宽区域。随后，开口可以用绝缘材料填充以形成隔离区域。晶体管器件然后可以形成在隔离区域的相对侧上，并且与隔离区域彼此电隔离。本发明还包括包含延伸到半导体材料中的电绝缘隔离结构的半导体结构，其结构具有球形底部区域和从底部区域向上延伸到半导体材料表面的杆区域。

3. 发明申请

US20060292838A1 Ion implanting methods 有权
标题翻译：离子注入方法
公开(公告)号：US20060292838A1
公开(公告)日：2006-12-28
申请号：US11168893
申请日：2005-06-28
申请人： Randall Culver , Terrence McDaniel , Hongmei Wang , James Dale , Richard Lane , Fred Fishburn
发明人： Randall Culver , Terrence McDaniel , Hongmei Wang , James Dale , Richard Lane , Fred Fishburn
IPC分类号： H01L21/22 , H01L21/31
CPC分类号： H01L21/26586 , H01L21/266
摘要： An ion implanting method includes forming a pair of spaced and adjacent features projecting outwardly from a substrate. At least outermost portions of the pair of spaced features are laterally pulled away from one another with a patterned photoresist layer received over the features and which has an opening therein received intermediate the pair of spaced features. While such spaced features are laterally pulled, a species is ion implanted into substrate material which is received lower than the pair of spaced features. After the ion implanting, the patterned photoresist layer is removed from the substrate. Other aspects and implementations are contemplated.
摘要翻译：离子注入方法包括形成从衬底向外突出的一对间隔且相邻的特征。所述一对间隔特征中的至少最外部的部分被横向地拉离彼此，图案化的光致抗蚀剂层被接收在特征上，并且其中具有开口，其中接收有一对隔开的特征。虽然这种间隔的特征被横向拉伸，但是一种物质被离子注入到被接收低于该对间隔特征的基底材料中。在离子注入之后，从衬底去除图案化的光致抗蚀剂层。考虑了其他方面和实现。

4. 发明申请

US20060199341A1 Methods of forming threshold voltage implant regions 失效
标题翻译：形成阈值电压注入区域的方法
公开(公告)号：US20060199341A1
公开(公告)日：2006-09-07
申请号：US11406893
申请日：2006-04-18
申请人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

5. 发明申请

US20060183291A1 Methods of forming capacitor structures 失效
公开(公告)号：US20060183291A1
公开(公告)日：2006-08-17
申请号：US11406862
申请日：2006-04-18
申请人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
IPC分类号： H01L21/425
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

6. 发明申请

US20050018381A1 Capacitor constructions and methods of forming 有权
公开(公告)号：US20050018381A1
公开(公告)日：2005-01-27
申请号：US10624340
申请日：2003-07-21
申请人： Brent McClure , Casey Kurth , Shenlin Chen , Debra Gould , Lyle Breiner , Er-Xuan Ping , Fred Fishburn , Hongmei Wang
发明人： Brent McClure , Casey Kurth , Shenlin Chen , Debra Gould , Lyle Breiner , Er-Xuan Ping , Fred Fishburn , Hongmei Wang
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/08 , H02H9/02
CPC分类号： H01L28/84 , H01L27/0805 , H01L27/10867 , H01L27/10873 , H01L28/75 , H01L28/91
摘要： A capacitor construction includes a first electrode and a layer between the first electrode and a surface supporting the capacitor construction. The capacitor construction can exhibit a lower RC time constant compared to an otherwise identical capacitor construction lacking the layer. Alternatively, or additionally, the first electrode may contain Si and the layer may limit the Si from contributing to formation of metal silicide material between the first electrode and the supporting surface. The layer may be a nitride layer and may be conductive or insulative. When conductive, the layer may exhibit a first conductivity greater than a second conductivity of the first electrode. The capacitor construction may be used in memory devices.

7. 发明申请

US20060046381A1 Methods of forming capacitor structures, methods of forming threshold voltage implant regions, and methods of implanting dopant into channel regions 失效
标题翻译：形成电容器结构的方法，形成阈值电压注入区域的方法以及将掺杂剂注入沟道区域的方法
公开(公告)号：US20060046381A1
公开(公告)日：2006-03-02
申请号：US10925736
申请日：2004-08-24
申请人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

8. 发明申请

US20060199340A1 Methods of implanting dopant into channel regions 有权
标题翻译：将掺杂剂注入通道区域的方法
公开(公告)号：US20060199340A1
公开(公告)日：2006-09-07
申请号：US11406863
申请日：2006-04-18
申请人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

9. 发明申请

US20050269669A1 Capacitor constructions and methods of forming 审中-公开
标题翻译：电容器结构和形成方法
公开(公告)号：US20050269669A1
公开(公告)日：2005-12-08
申请号：US11185468
申请日：2005-07-19
申请人： Brent McClure , Casey Kurth , Shenlin Chen , Debra Gould , Lyle Breiner , Er-Xuan Ping , Fred Fishburn , Hongmei Wang
发明人： Brent McClure , Casey Kurth , Shenlin Chen , Debra Gould , Lyle Breiner , Er-Xuan Ping , Fred Fishburn , Hongmei Wang
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/08 , H01L29/00
CPC分类号： H01L28/84 , H01L27/0805 , H01L27/10867 , H01L27/10873 , H01L28/75 , H01L28/91
摘要： A capacitor construction includes a first electrode and a layer between the first electrode and a surface supporting the capacitor construction. The capacitor construction can exhibit a lower RC time constant compared to an otherwise identical capacitor construction lacking the layer. Alternatively, or additionally, the first electrode may contain Si and the layer may limit the Si from contributing to formation of metal silicide material between the first electrode and the supporting surface. The layer may be a nitride layer and may be conductive or insulative. When conductive, the layer may exhibit a first conductivity greater than a second conductivity of the first electrode. The capacitor construction may be used in memory devices.
摘要翻译：电容器结构包括第一电极和第一电极与支撑电容器结构的表面之间的层。与其他相同的电容器结构相比，电容器结构可以表现出较低的RC时间常数。或者或另外，第一电极可以包含Si，并且该层可以限制Si对第一电极和支撑表面之间的金属硅化物材料的形成有贡献。该层可以是氮化物层，并且可以是导电的或绝缘的。当导电时，该层可以表现出大于第一电极的第二电导率的第一电导率。电容器结构可用于存储器件中。

10. 发明申请

US20060003182A1 Method for forming controlled geometry hardmasks including subresolution elements and resulting structures 有权
标题翻译：用于形成受控几何硬掩模的方法，包括分解元素和所得结构
公开(公告)号：US20060003182A1
公开(公告)日：2006-01-05
申请号：US10883215
申请日：2004-07-01
申请人： Richard Lane , Fred Fishburn
发明人： Richard Lane , Fred Fishburn
IPC分类号： B32B19/00 , H01L21/302
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088
摘要： Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of precise subresolution features useful for forming integrated circuits. The resulting symmetrical hardmask spacers with their symmetric upper portions may be used to accurately etch well-defined, high aspect ratio features in the underlying substrate. Some disclosed methods also enable simultaneous formation of hardmask structures of various dimensions, of both conventional and subresolution size, to enable etching structural features of different sizes in the underlying substrate.
摘要翻译：在诸如硅晶片或石英衬底之类的衬底上形成硬掩模材料的准确的对称横截面间隔物的方法，用于形成用于形成集成电路的精确的子分辨特征。所得到的对称硬掩模间隔物与其对称的上部可用于精确地蚀刻底层基底中的良好限定的高纵横比特征。一些公开的方法还能够同时形成具有常规和亚分辨率尺寸的各种尺寸的硬掩模结构，以使得能够蚀刻下面的衬底中的不同尺寸的结构特征。

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