专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050044032A1 Interactive bid evaluation system, method, and iconic interface for combinatorial auctions 审中-公开
标题翻译：互动竞价评估系统，方法和组合拍卖的标志性界面
公开(公告)号：US20050044032A1
公开(公告)日：2005-02-24
申请号：US10645609
申请日：2003-08-22
申请人： Ho Lee , Juhnyoung Lee , Jayant Kalagnanam , Sudhir Verma
发明人： Ho Lee , Juhnyoung Lee , Jayant Kalagnanam , Sudhir Verma
IPC分类号： G06Q30/00 , G06F17/60
CPC分类号： G06Q30/08 , G06Q40/04
摘要： An interactive bid evaluation system (method and storage medium) for a combinatorial auction, includes a display for scaling a plurality of bids and items, on a display window.
摘要翻译：用于组合拍卖的交互式出价评估系统（方法和存储介质）包括用于在显示窗口上缩放多个出价和项目的显示器。

2. 发明申请

US20080079086A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080079086A1
公开(公告)日：2008-04-03
申请号：US11831069
申请日：2007-07-31
申请人： Hyung-suk Jung , Jong-ho Lee , Sung-kee Han , Ho Lee , Ha-jin Lim
发明人： Hyung-suk Jung , Jong-ho Lee , Sung-kee Han , Ho Lee , Ha-jin Lim
IPC分类号： H01L21/336 , H01L27/085
CPC分类号： H01L21/823807
摘要： A semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device includes a semiconductor substrate in which PMOS transistor regions and NMOS transistor regions are formed, a PMOS transistor including P-type source and drain regions and a gate electrode, and an NMOS transistor formed on an Si channel region between N-type source and drain regions. The PMOS transistor is formed in each PMOS transistor region, and the gate electrode is formed on a high-dielectric gate insulating film formed on an SiGe channel region between the P-type source and drain regions. Further, the NMOS transistor includes a high-dielectric gate insulating film and a gate electrode formed on the gate insulating film, and the NMOS transistor is formed in each NMOS transistor region.
摘要翻译：一种半导体器件和半导体器件的制造方法，其中半导体器件包括其中形成有PMOS晶体管区域和NMOS晶体管区域的半导体衬底，包括P型源极和漏极区域的PMOS晶体管和栅极电极，以及形成在N型源区和漏区之间的Si沟道区上的NMOS晶体管。 PMOS晶体管形成在每个PMOS晶体管区域中，并且栅电极形成在形成在P型源区和漏区之间的SiGe沟道区上的高电介质栅极绝缘膜上。此外，NMOS晶体管包括高电介质栅极绝缘膜和形成在栅极绝缘膜上的栅电极，并且NMOS晶体管形成在每个NMOS晶体管区域中。

3. 发明授权

US08741710B2 Methods of fabricating semiconductor devices using a plasma process with non-silane gas including deuterium 有权
标题翻译：使用包括氘的非硅烷气体的等离子体处理制造半导体器件的方法
公开(公告)号：US08741710B2
公开(公告)日：2014-06-03
申请号：US12248431
申请日：2008-10-09
申请人： Dong-Suk Shin , Ho Lee , Tae-Gyun Kim
发明人： Dong-Suk Shin , Ho Lee , Tae-Gyun Kim
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/8238 , H01L21/28176 , H01L21/3003 , H01L21/76814 , H01L21/76826 , H01L21/76829 , H01L21/8234 , H01L21/823475 , H01L21/823871 , H01L29/665
摘要： Semiconductor devices are fabricated using a plasma process with a non-silane gas that includes deuterium, and which may result in improved device reliability and/or other improved device operational characteristics. One such method can include forming a gate oxide layer on a transistor region, which is defined on a substrate, and forming a gate electrode on the gate oxide layer. An etch stop layer is formed on the gate oxide layer and the gate electrode. A plasma process is performed on the interface between the gate oxide layer and the substrate using a non-silane treatment gas including deuterium. An interlayer dielectric layer is formed on the etch stop layer. A bottom metal line is formed on the interlayer dielectric layer.
摘要翻译：使用包括氘的非硅烷气体的等离子体工艺制造半导体器件，并且其可以导致改进的器件可靠性和/或其他改进的器件操作特性。一种这样的方法可以包括在限定在衬底上的晶体管区域上形成栅极氧化层，并在栅极氧化物层上形成栅电极。在栅极氧化物层和栅电极上形成蚀刻停止层。使用包括氘的非硅烷处理气体在栅极氧化物层和衬底之间的界面上进行等离子体处理。在蚀刻停止层上形成层间电介质层。底层金属线形成在层间电介质层上。

4. 发明授权

US07682888B2 Methods of forming NMOS/PMOS transistors with source/drains including strained materials 有权
标题翻译：用包括应变材料在内的源极/漏极形成NMOS / PMOS晶体管的方法
公开(公告)号：US07682888B2
公开(公告)日：2010-03-23
申请号：US11435968
申请日：2006-05-17
申请人： Ho Lee , Tetsuji Ueno , Hwa-Sung Rhe
发明人： Ho Lee , Tetsuji Ueno , Hwa-Sung Rhe
IPC分类号： H01L21/4763
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02211 , H01L21/02293 , H01L21/3147 , H01L21/3148 , H01L21/3185 , H01L21/823814 , H01L29/045 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A method of forming an integrated circuit includes selectively forming active channel regions for NMOS and PMOS transistors on a substrate parallel to a crystal orientation thereof and selectively forming source/drain regions of the NMOS transistors with Carbon (C) impurities therein.
摘要翻译：形成集成电路的方法包括：在与其100°晶体取向平行的衬底上选择性地形成用于NMOS和PMOS晶体管的有源沟道区，并且选择性地形成具有碳（C）杂质的NMOS晶体管的源极/漏极区。

5. 发明授权

US07671420B2 Semiconductor devices having faceted channels and methods of fabricating such devices 有权
标题翻译：具有小平面通道的半导体器件和制造这种器件的方法
公开(公告)号：US07671420B2
公开(公告)日：2010-03-02
申请号：US11281599
申请日：2005-11-18
申请人： Dong-Suk Shin , Ueno Tetsuji , Seung-Hwan Lee , Ho Lee , Hwa-Sung Rhee
发明人： Dong-Suk Shin , Ueno Tetsuji , Seung-Hwan Lee , Ho Lee , Hwa-Sung Rhee
IPC分类号： H01L29/76 , H01L27/148 , H01L27/01
CPC分类号： H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L29/045 , H01L29/66795 , H01L29/7851 , H01L29/7853
摘要： Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orientations. At least one of the surface regions will incorporate at least one faceted epitaxial semiconductor structure having surfaces that exhibit a crystal orientation different than the semiconductor region on which the faceted epitaxial semiconductor structure is formed. According, the crystal orientation in the channel regions of the NMOS and/or PMOS devices may be configured to improve the relative performance of at least one of the devices and allow corresponding redesign of the semiconductor devices fabricated using such a process.
摘要翻译：公开了用于制造用于制造半导体器件，特别是CMOS器件的半导体衬底的工艺和技术，其包括具有不同晶体取向的选择性地形成的高质量单晶或单晶表面区域。表面区域中的至少一个将结合至少一个具有不同于其上形成有刻面外延半导体结构的半导体区域的晶体取向的表面的分面外延半导体结构。根据，NMOS和/或PMOS器件的沟道区域中的晶体取向可以被配置为改善至少一个器件的相对性能，并允许对使用这种工艺制造的半导体器件进行相应的重新设计。

6. 发明授权

US07611973B2 Methods of selectively forming epitaxial semiconductor layer on single crystalline semiconductor and semiconductor devices fabricated using the same 有权
标题翻译：在使用其制造的单晶半导体和半导体器件上选择性地形成外延半导体层的方法
公开(公告)号：US07611973B2
公开(公告)日：2009-11-03
申请号：US11154236
申请日：2005-06-16
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/28044 , H01L21/02378 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/66628 , H01L29/66772
摘要： In methods of selectively forming an epitaxial semiconductor layer on a single crystalline semiconductor and semiconductor devices fabricated using the same, a single crystalline epitaxial semiconductor layer and a non-single crystalline epitaxial semiconductor layer are formed on a single crystalline semiconductor and a non-single crystalline semiconductor pattern respectively, using a main semiconductor source gas and a main etching gas. The non-single crystalline epitaxial semiconductor layer is removed using a selective etching gas. The main gases and the selective etching gas are alternately and repeatedly supplied at least two times to selectively form an elevated single crystalline epitaxial semiconductor layer having a desired thickness only on the single crystalline semiconductor. The selective etching gas suppresses formation of an epitaxial semiconductor layer on the non-single crystalline semiconductor pattern.
摘要翻译：在单晶半导体上选择性地形成外延半导体层的方法和使用其制造的半导体器件的方法中，单晶外延半导体层和非单晶外延半导体层形成在单晶半导体和非单晶半导体图案，分别使用主半导体源气体和主蚀刻气体。使用选择性蚀刻气体去除非单晶外延半导体层。主要气体和选择性蚀刻气体交替地和重复地供应至少两次以选择性地形成仅在单晶半导体上具有期望厚度的升高的单晶外延半导体层。选择性蚀刻气体抑制在非单晶半导体图案上形成外延半导体层。

7. 发明申请

US20090258463A1 METHODS OF FABRICATING DIFFERENT THICKNESS SILICON-GERMANIUM LAYERS ON SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES FABRICATED THEREBY 有权
标题翻译：在半导体集成电路器件和半导体集成电路器件上制造不同厚度的硅 - 锗层的方法
公开(公告)号：US20090258463A1
公开(公告)日：2009-10-15
申请号：US12419698
申请日：2009-04-07
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/20 , H01L21/768
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
摘要翻译：提供制造半导体集成电路器件的方法。基板设置有形成在第一和第二区域上的栅极图案。第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。直接在第一SiGe外延层上形成第二SiGe外延层，以使用不同于第一硅源气体的第二硅源气体来进一步填充源/漏沟槽。

8. 发明申请

US20090224287A1 SEMICONDUCTOR DEVICE HAVING A LOCALLY BURIED INSULATION LAYER 审中-公开
标题翻译：具有局部绝缘绝缘层的半导体器件
公开(公告)号：US20090224287A1
公开(公告)日：2009-09-10
申请号：US12400408
申请日：2009-03-09
申请人： Dong-Suk Shin , Ho Lee , Myung-Sun Kim
发明人： Dong-Suk Shin , Ho Lee , Myung-Sun Kim
IPC分类号： H01L29/80
CPC分类号： H01L29/1083 , H01L21/76267 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A semiconductor device having a locally buried insulation layer and a method of manufacturing a semiconductor device having the same are provided, in which a gate electrode is formed on a substrate, and oxygen ions are implanted into an active region to form a locally buried insulation layer. An impurity layer is formed on the locally buried insulation layer to form a source/drain. A silicide layer is formed on the source/drain and on the gate electrode. The locally buried insulation layer can prevent junction leakage, decrease junction capacitance and prevent a critical voltage of an MOS transistor from increasing due to body bias, thereby to improve characteristics of the device.
摘要翻译：提供了具有局部掩埋绝缘层的半导体器件及其制造方法，其中在基板上形成栅电极，并将氧离子注入有源区以形成局部掩埋的绝缘层。在局部掩埋的绝缘层上形成杂质层以形成源极/漏极。在源极/漏极和栅电极上形成硅化物层。局部埋入绝缘层可以防止结漏电，降低结电容，并防止MOS晶体管的临界电压由于体偏压而增加，从而改善器件的特性。

9. 发明申请

US20090194736A1 Nanosized nickel-doped carbon nanotubes for hydrogen storage and production method thereof 审中-公开
标题翻译：用于氢存储的纳米镍掺杂碳纳米管及其制备方法
公开(公告)号：US20090194736A1
公开(公告)日：2009-08-06
申请号：US11396910
申请日：2006-04-04
申请人： Jai-Young Lee , Jeung-Ku Kang , Hyun-Seok Kim , Kyu-Sung Han , Min-Sang Song , Ho Lee , Jin-Ho Kim
发明人： Jai-Young Lee , Jeung-Ku Kang , Hyun-Seok Kim , Kyu-Sung Han , Min-Sang Song , Ho Lee , Jin-Ho Kim
IPC分类号： C09K3/00 , B01J13/02
CPC分类号： H01M8/04216 , B01J20/0225 , B01J20/20 , B01J20/205 , B01J20/3204 , B01J20/3236 , B01J20/3295 , B82Y30/00 , B82Y40/00 , C01B3/0021 , C01B32/162 , C01B32/168 , F17C11/005 , H01M8/0612 , Y02E60/321 , Y02E60/325
摘要： Disclosed herein is a method of doping nanosized nickel (Ni) on the surface of carbon nanotubes to improve the hydrogen storage capacity of the carbon nanotubes. The method comprises: sonicating carbon nanotube samples produced by vapor deposition, in sulfuric acid solution, followed by filtration to remove a metal catalyst from the carbon nanotube samples; and doping the carbon nanotube samples in liquid phase solution, followed by drying and reduction, so as to dope nanosized nickel on the surface of the carbon nanotubes.
摘要翻译：本文公开了在纳米碳管表面掺杂纳米尺寸镍（Ni）以提高碳纳米管的储氢能力的方法。该方法包括：在硫酸溶液中超声处理气相沉积产生的碳纳米管样品，然后过滤以从碳纳米管样品中除去金属催化剂; 并将碳纳米管样品掺杂在液相中，然后进行干燥和还原，从而将纳米尺寸的镍掺杂在碳纳米管的表面上。

10. 发明授权

US07439596B2 Transistors for semiconductor device and methods of fabricating the same 有权
标题翻译：用于半导体器件的晶体管及其制造方法
公开(公告)号：US07439596B2
公开(公告)日：2008-10-21
申请号：US11045060
申请日：2005-01-31
申请人： Jae-Yoon Yoo , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee , Hyun-Suk Kim , Moon-Han Park
发明人： Jae-Yoon Yoo , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee , Hyun-Suk Kim , Moon-Han Park
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66537 , H01L29/1083 , H01L29/665 , H01L29/66545 , H01L29/66553 , H01L29/6659 , H01L29/7833
摘要： The present invention discloses a transistor for a semiconductor device capable of preventing the generation of a depletion capacitance in a gate pattern due to the diffusion of impurity ions. The present invention also discloses a method of fabricating the transistor.
摘要翻译：本发明公开了一种用于半导体器件的晶体管，其能够防止由于杂质离子的扩散而产生栅极图案中的耗尽电容。本发明还公开了一种制造晶体管的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式