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1. 发明授权

US06972458B2 Horizontal MOS transistor 失效
标题翻译：水平MOS晶体管
公开(公告)号：US06972458B2
公开(公告)日：2005-12-06
申请号：US10729955
申请日：2003-12-09
申请人： Naohiro Suzuki , Jun Sakakibara , Yoshitaka Noda , Hitoshi Yamaguchi
发明人： Naohiro Suzuki , Jun Sakakibara , Yoshitaka Noda , Hitoshi Yamaguchi
IPC分类号： H01L29/41 , H01L21/336 , H01L21/8222 , H01L21/8234 , H01L21/8248 , H01L21/8249 , H01L21/84 , H01L27/06 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/49 , H01L29/732 , H01L29/739 , H01L29/76 , H01L29/78 , H01L29/786 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/66681 , H01L29/7394 , H01L29/7824 , H01L29/7825
摘要： A semiconductor device includes a base P region, a source N+ region, and a drain N+ region formed in a surface layer portion on a principal surface in an N− silicon layer. In the surface layer portion on the principal surface, an N well region is formed deeper than the drain N+ region in a region including the drain N+ region and is in contact with the base P region. A trench is formed so as to penetrate the base P region in a direction toward the drain N+ region from the source N+ region as a planar structure. A gate electrode is formed via a gate insulating film in the inside of the trench.
摘要翻译：半导体器件包括在N - 硅层。在主表面的表层部分，在包括漏极N + SUP区域的区域中，N阱区形成得比漏极N + + SUP区域深，并与之接触与基地区P。形成沟槽，以从源极N +区域的漏极N + SUP区域的方向穿过基极P区域作为平面结构。栅极电极通过沟槽内部的栅极绝缘膜形成。

2. 发明授权

US06439514B1 Semiconductor device with elements surrounded by trenches 有权
标题翻译：具有由沟槽围绕的元件的半导体器件
公开(公告)号：US06439514B1
公开(公告)日：2002-08-27
申请号：US09493937
申请日：2000-01-28
申请人： Hitoshi Yamaguchi , Yoshitaka Noda
发明人： Hitoshi Yamaguchi , Yoshitaka Noda
IPC分类号： H01L2900
CPC分类号： H01L29/41758 , H01L21/76264 , H01L21/76283 , H01L27/1203 , H01L29/0696 , H01L29/7394 , H01L29/7398 , H01L29/7824
摘要： Pch-MOS transistors to which a power supply potential is applied are respectively surrounded by first trenches, and Nch-MOS transistors to which a ground potential is applied are respectively surrounded by second trenches. The first trenches are surrounded by a third trench, and the second trenches are surrounded by a fourth trench. A silicon layer existing inside the third trench is set at the power source potential. The silicon layer existing between the third and fourth trenches are set at a floating state. Accordingly, each thickness of oxide layers filling the trenches can be reduced.
摘要翻译：施加电源电位的Pch-MOS晶体管分别被第一沟槽环绕，并且施加有接地电位的Nch-MOS晶体管分别被第二沟槽包围。第一沟槽被第三沟槽围绕，第二沟槽被第四沟槽围绕。存在于第三沟槽内的硅层设置在电源电位。存在于第三沟槽和第四沟槽之间的硅层被设置为浮置状态。因此，可以减少填充沟槽的氧化物层的每个厚度。

3. 发明申请

US20050230747A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050230747A1
公开(公告)日：2005-10-20
申请号：US11156451
申请日：2005-06-21
申请人： Naohiro Suzuki , Jun Sakakibara , Yoshitaka Noda , Hitoshi Yamaguchi
发明人： Naohiro Suzuki , Jun Sakakibara , Yoshitaka Noda , Hitoshi Yamaguchi
IPC分类号： H01L29/41 , H01L21/336 , H01L21/8222 , H01L21/8234 , H01L21/8248 , H01L21/8249 , H01L21/84 , H01L27/06 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/49 , H01L29/732 , H01L29/739 , H01L29/76 , H01L29/78 , H01L29/786 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/66681 , H01L29/7394 , H01L29/7824 , H01L29/7825
摘要： A semiconductor device includes a base P region, a source N+ region, and a drain N+ region formed in a surface layer portion on a principal surface in an N− silicon layer. In the surface layer portion on the principal surface, an N well region is formed deeper than the drain N+ region in a region including the drain N+ region and is in contact with the base P region. A trench is formed so as to penetrate the base P region in a direction toward the drain N+ region from the source N+ region as a planar structure. A gate electrode is formed via a gate insulating film in the inside of the trench.
摘要翻译：半导体器件包括在N - 硅层。在主表面的表层部分，在包括漏极N + SUP区域的区域中，N阱区形成得比漏极N + + SUP区域深，并与之接触与基地区P。形成沟槽，以从源极N +区域的漏极N + SUP区域的方向穿过基极P区域作为平面结构。栅极电极通过沟槽内部的栅极绝缘膜形成。

4. 发明授权

US07948349B2 Magnetic coupler 有权
标题翻译：磁耦合器
公开(公告)号：US07948349B2
公开(公告)日：2011-05-24
申请号：US12289384
申请日：2008-10-27
申请人： Susumu Haratani , Hitoshi Yamaguchi
发明人： Susumu Haratani , Hitoshi Yamaguchi
IPC分类号： H01F17/04
CPC分类号： G01R33/09 , G01R33/091 , H01F5/003 , H01F38/14
摘要： A magnetic coupler having higher response is provided. The magnetic coupler includes a thin film coil wound in a first layer; a first MR element being disposed in a second layer, and detecting an induced magnetic field generated by a signal current flowing through the thin film coil; and yokes being disposed close to the first MR element, and including a soft magnetic material. The first MR element is disposed in a position corresponding to a linear region of the thin film coil in a stacking direction. The yokes are disposed at both of an inner turn side and an outer turn side of the thin film coil in a manner of interposing the first MR element in the second layer. Thus, reduction in intensity of the induced magnetic field is suppressed, and intensity distribution of the induced magnetic field becomes flatter.
摘要翻译：提供了具有较高响应的磁耦合器。磁耦合器包括缠绕在第一层中的薄膜线圈; 第一MR元件设置在第二层中，并且检测由流过薄膜线圈的信号电流产生的感应磁场; 并且轭设置成靠近第一MR元件，并且包括软磁材料。第一MR元件被布置在与层叠方向上的薄膜线圈的线性区域对应的位置。磁轭以将第一MR元件插入第二层的方式设置在薄膜线圈的内侧转弯侧和外侧转动侧。因此，抑制感应磁场强度的降低，感应磁场的强度分布变得更平坦。

5. 发明授权

US07928470B2 Semiconductor device having super junction MOS transistor and method for manufacturing the same 有权
标题翻译：具有超结MOS晶体管的半导体器件及其制造方法
公开(公告)号：US07928470B2
公开(公告)日：2011-04-19
申请号：US11598646
申请日：2006-11-14
申请人： Hitoshi Yamaguchi , Jun Sakakibara
发明人： Hitoshi Yamaguchi , Jun Sakakibara
IPC分类号： H01L29/66
CPC分类号： H01L29/66712 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813
摘要： A semiconductor device having a super junction MOS transistor includes: a semiconductor substrate; a first semiconductor layer on the substrate; a second semiconductor layer on the first semiconductor layer; a channel forming region on a first surface portion of the second semiconductor layer; a source region on a first surface portion of the channel forming region; a source contact region on a second surface portion of the channel forming region; a gate electrode on a third surface portion of the channel forming region; a source electrode on the source region and the source contact region; a drain electrode on a backside of the substrate; and an anode electrode on a second surface portion of the second semiconductor layer. The anode electrode provides a Schottky barrier diode.
摘要翻译：具有超结MOS晶体管的半导体器件包括：半导体衬底; 在所述基板上的第一半导体层; 在所述第一半导体层上的第二半导体层; 在第二半导体层的第一表面部分上的沟道形成区; 在所述沟道形成区域的第一表面部分上的源极区域; 在所述沟道形成区域的第二表面部分上的源极接触区域; 在沟道形成区域的第三表面部分上的栅电极; 源极区域和源极接触区域上的源极电极; 位于衬底背面的漏电极; 以及在所述第二半导体层的第二表面部分上的阳极电极。阳极电极提供肖特基势垒二极管。

6. 发明授权

US07858475B2 Method for manufacturing a vertical transistor that includes a super junction structure 有权
标题翻译：一种制造包括超结结构的垂直晶体管的方法
公开(公告)号：US07858475B2
公开(公告)日：2010-12-28
申请号：US12614632
申请日：2009-11-09
申请人： Hitoshi Yamaguchi , Takeshi Miyajima , Nozomu Akagi
发明人： Hitoshi Yamaguchi , Takeshi Miyajima , Nozomu Akagi
IPC分类号： H01L21/8234
CPC分类号： H01L29/7813 , H01L21/823814 , H01L21/823885 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/1095 , H01L29/66734 , H01L29/7803 , H01L29/7811 , Y10S438/977
摘要： A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench, the first and second columns alternately repeated along with a predetermined direction; thinning a second side of the substrate; and increasing an impurity concentration in a thinned second side so that a first conductive type layer is provided. The impurity concentration of the first conductive type layer is higher than the first column. The first column provides a drift layer so that a vertical type first-conductive-type channel transistor is formed.
摘要翻译：半导体器件的制造方法包括：在半导体衬底上形成多个沟槽; 在每个沟槽中形成第二导电类型的半导体膜，以提供具有在两个沟槽之间的衬底的第一柱和在沟槽中的第二导电型半导体膜的第二柱，第一和第二列与预定方向交替地重复; 减薄基板的第二面; 并增加稀薄第二侧的杂质浓度，从而提供第一导电类型层。第一导电型层的杂质浓度比第一列高。第一列提供漂移层，从而形成垂直型第一导电型沟道晶体管。

7. 发明申请

US20100248623A1 Signal transmission device 有权
标题翻译：信号传输装置
公开(公告)号：US20100248623A1
公开(公告)日：2010-09-30
申请号：US12659795
申请日：2010-03-22
申请人： Susumu Haratani , Hitoshi Yamaguchi , Masahiro Miyazaki , Yoshio Sase , Shigeru Shimura
发明人： Susumu Haratani , Hitoshi Yamaguchi , Masahiro Miyazaki , Yoshio Sase , Shigeru Shimura
IPC分类号： H04B1/02
CPC分类号： H04B5/0031 , H04B5/0081
摘要： A signal transmission device includes: an input signal conductor in which an input signal current flows and thereby generating an input signal magnetic field; a magnetically-biasing conductor in which a biasing current flows and thereby generating a biasing magnetic field; and one or more magnetoresistive elements in each of which a sensing current flows and thereby generating a self-biasing magnetic field, and each including a magnetization free layer having a magnetization direction which varies in response to the input signal magnetic field, the biasing magnetic field, and the self-biasing magnetic field. Each of the biasing magnetic field and the self-biasing magnetic field is applied to the magnetization free layer in a same direction to each other.
摘要翻译：信号传输装置包括：输入信号导体，其中输入信号电流流动，从而产生输入信号磁场; 磁偏置导体，其中偏置电流流动，从而产生偏置磁场; 以及一个或多个磁阻元件，其中每一个感测电流流动，从而产生自偏置磁场，并且每个磁阻元件包括响应于输入信号磁场而变化的磁化方向的磁化自由层，偏置磁场，和自偏磁场。偏置磁场和自偏磁场中的每一个以彼此相同的方向施加到磁化自由层。

8. 发明授权

US07635622B2 Method for manufacturing a vertical transistor that includes a super junction structure 有权
标题翻译：一种制造包括超结结构的垂直晶体管的方法
公开(公告)号：US07635622B2
公开(公告)日：2009-12-22
申请号：US11889075
申请日：2007-08-09
申请人： Hitoshi Yamaguchi , Takeshi Miyajima
发明人： Hitoshi Yamaguchi , Takeshi Miyajima
IPC分类号： H01L21/8238
CPC分类号： H01L29/7813 , H01L21/823814 , H01L21/823885 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/1095 , H01L29/66734 , H01L29/7803 , H01L29/7811 , Y10S438/977
摘要： A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench, the first and second columns alternately repeated along with a predetermined direction; thinning a second side of the substrate; and increasing an impurity concentration in a thinned second side so that a first conductive type layer is provided. The impurity concentration of the first conductive type layer is higher than the first column. The first column provides a drift layer so that a vertical type first-conductive-type channel transistor is formed.
摘要翻译：半导体器件的制造方法包括：在半导体衬底上形成多个沟槽; 在每个沟槽中形成第二导电类型的半导体膜，以提供具有在两个沟槽之间的衬底的第一柱和在沟槽中的第二导电型半导体膜的第二柱，第一和第二列与预定方向交替地重复; 减薄基板的第二面; 并增加稀薄第二侧的杂质浓度，从而提供第一导电类型层。第一导电型层的杂质浓度比第一列高。第一列提供漂移层，从而形成垂直型第一导电型沟道晶体管。

9. 发明授权

US07601603B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07601603B2
公开(公告)日：2009-10-13
申请号：US11094782
申请日：2005-03-31
申请人： Shoichi Yamauchi , Hitoshi Yamaguchi , Tomoatsu Makino , Syouji Nogami , Tomonori Yamaoka
发明人： Shoichi Yamauchi , Hitoshi Yamaguchi , Tomoatsu Makino , Syouji Nogami , Tomonori Yamaoka
IPC分类号： H01L21/20
CPC分类号： H01L29/7813 , H01L21/823487 , H01L29/0634 , H01L29/7811
摘要： A method for manufacturing a semiconductor device includes the steps of: forming a trench in a semiconductor substrate; and forming an epitaxial film on the substrate including a sidewall and a bottom of the trench so that the epitaxial film is filled in the trench. The step of forming the epitaxial film includes a final step before the trench is filled with the epitaxial film. The final step has a forming condition of the epitaxial film in such a manner that the epitaxial film to be formed on the sidewall of the trench has a growth rate at an opening of the trench smaller than a growth rate at a position of the trench, which is deeper than the opening of the trench.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底中形成沟槽; 以及在包括沟槽的侧壁和底部的衬底上形成外延膜，使得外延膜填充在沟槽中。形成外延膜的步骤包括在沟槽被外延膜填充之前的最后步骤。最终步骤具有外延膜的形成条件，使得形成在沟槽的侧壁上的外延膜在沟槽的开口处的生长速率小于沟槽位置处的生长速率，其比沟槽的开口更深。

10. 发明授权

US07564095B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07564095B2
公开(公告)日：2009-07-21
申请号：US11439971
申请日：2006-05-25
申请人： Yasushi Urakami , Jun Sakakibara , Hitoshi Yamaguchi
发明人： Yasushi Urakami , Jun Sakakibara , Hitoshi Yamaguchi
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/66704 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7823 , H01L29/7825
摘要： A semiconductor device includes: a semiconductor substrate; an element region having a semiconductor element including an impurity layer and a trench, wherein the impurity layer is disposed in the trench, and wherein the trench is disposed on a main surface of the substrate; and a field region disposed around the element region. The trench is an aggregation of a plurality of stripe line trenches so that the element region has a polygonal shape. The field region includes a dummy trench disposed along with one side of the polygonal shape on a periphery of the element region. The dummy trench has a width and a longitudinal direction, which are equal to those of the trench. The field region further includes an impurity layer disposed in the dummy trench.
摘要翻译：半导体器件包括：半导体衬底; 具有包括杂质层和沟槽的半导体元件的元件区，其中所述杂质层设置在所述沟槽中，并且其中所述沟槽设置在所述衬底的主表面上; 以及设置在所述元件区域周围的场区域。沟槽是多个条纹沟槽的聚集，使得元件区域具有多边形形状。场区域包括在元件区域的周边上与多边形形状的一侧一起设置的虚拟沟槽。虚拟沟槽具有与沟槽相同的宽度和纵向方向。场区域还包括设置在虚拟沟槽中的杂质层。

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