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1. 发明授权

US06570580B1 Apparatus and method for information display 有权
标题翻译：信息显示装置及方法
公开(公告)号：US06570580B1
公开(公告)日：2003-05-27
申请号：US09440286
申请日：1999-11-15
申请人： Hitoshi Suzuki , Naohisa Koizumi , Goro Ohnishi , Tomohisa Kohiyama , Kazushi Kobayashi , Takeshi Igarashi , Hironori Oikawa , Hiroyuki Mano
发明人： Hitoshi Suzuki , Naohisa Koizumi , Goro Ohnishi , Tomohisa Kohiyama , Kazushi Kobayashi , Takeshi Igarashi , Hironori Oikawa , Hiroyuki Mano
IPC分类号： G09G524
CPC分类号： G06F3/1446 , Y10S715/963
摘要： An apparatus for information display for displaying not only periodic information in accordance with schedule, but also non-periodic information regardless of the schedule, to passengers and passersby in stations, airports, harbors, bus terminals and streets, and the like. The apparatus comprises an information-storing section for storing a plurality of non-periodic information to be displayed regardless of the schedule, an input circuit for receiving a plurality of input signals transmitted from an external device or a remote place and display control section for simultaneously displaying the non-periodic information and periodic information which correspond to the kind of an input signal, when the apparatus receives this input signal from the external apparatus or the remote place. The apparatus may be a multi-screen display type having a plurality of screens. In this case, a combined screen data consisting of a non-periodic information and a periodic information can be displayed, or the non-periodic information or the periodic information can be displayed, on at least one of the screens.
摘要翻译：一种用于信息显示的装置，不仅根据时间表显示周期性信息，而且还可以不依赖于时间表显示非周期性信息给站，机场，港口，公共汽车站和街道等中的乘客和路人。该装置包括一个信息存储部分，用于存储要被显示的多个非周期性信息，而不管时间表如何;输入电路，用于接收从外部设备或远程位置发送的多个输入信号以及同时显示控制部分当设备从外部设备或远程位置接收到该输入信号时，显示与输入信号的种类相对应的非周期信息和周期性信息。该装置可以是具有多个屏幕的多屏显示类型。在这种情况下，可以在至少一个屏幕上显示由非周期性信息和周期性信息组成的组合屏幕数据，或者可以显示非周期性信息或周期性信息。

2. 发明授权

US07802045B2 Bus system for use with information processing apparatus 失效
标题翻译：与信息处理设备一起使用的总线系统
公开(公告)号：US07802045B2
公开(公告)日：2010-09-21
申请号：US12501684
申请日：2009-07-13
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

3. 发明授权

US07577781B2 Bus system for use with information processing apparatus 失效
公开(公告)号：US07577781B2
公开(公告)日：2009-08-18
申请号：US12155047
申请日：2008-05-29
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

4. 发明授权

US07398346B2 Bus system for use with information processing apparatus 失效
标题翻译：与信息处理设备一起使用的总线系统
公开(公告)号：US07398346B2
公开(公告)日：2008-07-08
申请号：US11543878
申请日：2006-10-06
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

5. 发明授权

US5889971A Bus system for use with information processing apparatus 失效
公开(公告)号：US5889971A
公开(公告)日：1999-03-30
申请号：US959913
申请日：1997-10-29
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/16 , G06F12/00 , G06F13/36 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

6. 发明授权

US5483642A Bus system for use with information processing apparatus 失效
公开(公告)号：US5483642A
公开(公告)日：1996-01-09
申请号：US311893
申请日：1994-09-26
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/16 , G06F12/00 , G06F13/36 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

7. 发明授权

US5223459A Working system for aeroplane 失效
标题翻译：飞机工作系统
公开(公告)号：US5223459A
公开(公告)日：1993-06-29
申请号：US714670
申请日：1991-06-13
申请人： Shiro Odawara , Keiichi Ito , Kazushi Kobayashi
发明人： Shiro Odawara , Keiichi Ito , Kazushi Kobayashi
IPC分类号： B64F5/00 , E04B1/346 , E04H6/44
CPC分类号： B64F5/0009 , E04B1/346 , E04H6/44 , Y02P70/585
摘要： A working system for an aeroplane comprising a hangar for accommodating the aeroplane, a partition wall provided within the hangar for partitioning the hangar into a fuselage work area around a fuselage of the aeroplane and a main wing work area around a main wing, and working tables arranged in the fuselage work area. The partition wall is movable between a predetermined partitioning position and a retracted position allowing entrance and exit of the aeroplane. The working tables are movable within the fuselage work area separately from the partition wall.
摘要翻译：一种用于飞机的工作系统，包括用于容纳飞机的机库，设置在机库内的分隔壁，用于将机库分隔成机身的机身周围的机身工作区域和主翼周围的主翼工作区域以及工作台安排在机身工作区。分隔壁可以在预定的分隔位置和允许飞机进出的缩回位置之间移动。工作台可以在机身工作区域内与隔墙分开移动。

8. 发明申请

US20080071060A1 Surfactant Composition 有权
标题翻译：表面活性剂组成
公开(公告)号：US20080071060A1
公开(公告)日：2008-03-20
申请号：US11629655
申请日：2005-09-09
申请人： Kazushi Kobayashi , Koji Beppu
发明人： Kazushi Kobayashi , Koji Beppu
IPC分类号： C08G67/00
CPC分类号： C08F2/24 , B01F17/005
摘要： A surfactant composition has good emulsifiability for monomer(s), and can provide a polymer emulsion (herein after simply called “the emulsion”) of good stability while decreasing coagulations of polymer particles in the emulsion. The surfactant composition contains the following components (A) and (B): (A) a reactive surfactant containing at least one polymerizable double-bond group and at least one ionic group in a molecule, and (B) a nitrogen compound insoluble or slightly soluble in ethanol. A weight ratio (A:B) of the component (A) to the component (B) is from 100:0.03 to 100:1.0.
摘要翻译：表面活性剂组合物对于单体具有良好的乳化性，并且可以提供具有良好稳定性的聚合物乳液（这里简称为“乳液”），同时降低乳液中聚合物颗粒的凝结。表面活性剂组合物含有下列组分（A）和（B）：（A）分子中含有至少一个可聚合双键基团和至少一个离子基团的反应性表面活性剂，（B）不溶于或稍微溶于乙醇。成分（A）与成分（B）的重量比（A:B）为100:0.03〜100:1.0。

9. 发明授权

US06907489B2 Bus system for use with information processing apparatus 失效
标题翻译：与信息处理设备一起使用的总线系统
公开(公告)号：US06907489B2
公开(公告)日：2005-06-14
申请号：US10787110
申请日：2004-02-27
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

10. 发明授权

US5935231A Bus system for use with information processing apparatus 有权
公开(公告)号：US5935231A
公开(公告)日：1999-08-10
申请号：US143985
申请日：1998-08-31
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/16 , G06F12/00 , G06F13/36 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

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