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1. 发明授权

US07229569B1 Etching reagent, and method for manufacturing electronic device substrate and electronic device 有权
公开(公告)号：US07229569B1
公开(公告)日：2007-06-12
申请号：US09595415
申请日：2000-06-16
申请人： Hitoshi Seki , Jo Gyoo Chul
发明人： Hitoshi Seki , Jo Gyoo Chul
IPC分类号： C09K13/00
CPC分类号： C23F1/18 , C23F1/26 , H01L21/28568 , H01L21/32134 , H01L23/53238 , H01L27/124 , H01L29/458 , H01L29/4908 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an etching agent that is able to etch a Cu film by a simple chemical etching method such as an immersion method when the low resistance Cu film is used for a wiring material, while allowing time-dependent changes of the etching rate to be small and preventing a pattern narrowing phenomenon ascribed to irregular amount of side etching of the Cu film from occurring, by providing an etching agent comprising an aqueous solution containing potassium hydrogen peroxosulfate and hydrofluoric acid, wherein masks of a give pattern is formed on the surface of a laminated film prepared by sequentially depositing a Ti or Ti alloy film and a Cu film on a substrate, and wherein a gate electrode (a laminated wiring) and a lower pad layer (a laminated wiring) with give patterns are formed by etching the laminated film using the etching agent having the foregoing construction.

2. 发明授权

US07442324B2 Etching reagent, and method for manufacturing electronic device substrate and electronic device 有权
标题翻译：蚀刻试剂，以及电子器件基板和电子器件的制造方法
公开(公告)号：US07442324B2
公开(公告)日：2008-10-28
申请号：US11810365
申请日：2007-06-05
申请人： Hitoshi Seki , Jo Gyoo Chul
发明人： Hitoshi Seki , Jo Gyoo Chul
IPC分类号： C09K13/00
CPC分类号： C23F1/18 , C23F1/26 , H01L21/28568 , H01L21/32134 , H01L23/53238 , H01L27/124 , H01L29/458 , H01L29/4908 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an etching agent that is able to etch a Cu film by a simple chemical etching method such as an immersion method when the low resistance Cu film is used for a wiring material, while allowing time-dependent changes of the etching rate to be small and preventing a pattern narrowing phenomenon ascribed to irregular amount of side etching of the Cu film from occurring, by providing an etching agent comprising an aqueous solution containing potassium hydrogen peroxosulfate and hydrofluoric acid, wherein masks of a give pattern is formed on the surface of a laminated film prepared by sequentially depositing a Ti or Ti alloy film and a Cu film on a substrate, and wherein a gate electrode (a laminated wiring) and a lower pad layer (a laminated wiring) with give patterns are formed by etching the laminated film using the etching agent having the foregoing construction.
摘要翻译：本发明提供了一种蚀刻剂，其能够通过简单的化学蚀刻方法（例如当低电阻Cu膜用于布线材料时的浸渍法）蚀刻Cu膜，同时允许蚀刻速率随时间变化通过提供包含含有过氧硫酸氢钾和氢氟酸的水溶液的蚀刻剂，防止由于Cu膜的侧蚀而造成的不规则的图案变窄现象，其中在表面上形成赋型图案的掩模通过在基板上依次沉积Ti或Ti合金膜和Cu膜而制备的层压膜，其中通过蚀刻形成具有赋予图案的栅电极（层叠布线）和下焊盘层（层叠布线）使用具有上述结构的蚀刻剂的层叠膜。

3. 发明授权

US06852998B2 Thin-film transistor substrate and liquid crystal display 有权
标题翻译：薄膜晶体管基板和液晶显示器
公开(公告)号：US06852998B2
公开(公告)日：2005-02-08
申请号：US10385377
申请日：2003-03-07
申请人： Chae Gee Sung , Jo Gyoo Chul , Makoto Sasaki , Kazuyuki Arai
发明人： Chae Gee Sung , Jo Gyoo Chul , Makoto Sasaki , Kazuyuki Arai
IPC分类号： G09F9/30 , G02F1/1343 , G02F1/136 , G02F1/1362 , G02F1/1368 , G09F9/00 , H01L21/336 , H01L21/77 , H01L27/12 , H01L29/45 , H01L29/786 , H01L29/12
CPC分类号： H01L27/124 , G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/1214 , H01L29/458 , H01L29/66757
摘要： A source line is directly connected to a source terminal composed of indium zinc oxide in a thin-film transistor substrate. A gate line is directly connected to a gate terminal composed of indium zinc oxide. Alternatively, drain electrodes of thin-film transistors for switching a plurality of pixel electrodes are directly connected to pixel electrodes composed of indium zinc oxide. These configurations do not require a passivation film which is essential for conventional thin-film transistor substrates, and the resulting thin-film transistor substrate can be made by a reduced number of manufacturing steps.
摘要翻译：源极线直接连接到由薄膜晶体管衬底中的氧化铟锌构成的源极端子。栅极线直接连接到由氧化铟锌构成的栅极端子。或者，用于切换多个像素电极的薄膜晶体管的漏极直接连接到由氧化铟锌构成的像素电极。这些配置不需要对于传统的薄膜晶体管衬底是必需的钝化膜，并且所得到的薄膜晶体管衬底可以通过减少数量的制造步骤来制造。

4. 发明授权

US06649936B1 Thin-film transistor substrate and liquid crystal display 有权
标题翻译：薄膜晶体管基板和液晶显示器
公开(公告)号：US06649936B1
公开(公告)日：2003-11-18
申请号：US09526150
申请日：2000-03-15
申请人： Chae Gee Sung , Jo Gyoo Chul , Makoto Sasaki , Kazuyuki Arai
发明人： Chae Gee Sung , Jo Gyoo Chul , Makoto Sasaki , Kazuyuki Arai
IPC分类号： H01L310392
CPC分类号： H01L27/124 , G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/1214 , H01L29/458 , H01L29/66757
摘要： A source line is directly connected to a source terminal composed of indium zinc oxide in a thin-film transistor substrate. A gate line is directly connected to a gate terminal composed of indium zinc oxide. Alternatively, drain electrodes of thin-film transistors for switching a plurality of pixel electrodes are directly connected to pixel electrodes composed of indium zinc oxide. These configurations do not require a passivation film which is essential for conventional thin-film transistor substrates, and the resulting thin-film transistor substrate can be made by a reduced number of manufacturing steps.
摘要翻译：源极线直接连接到由薄膜晶体管衬底中的氧化铟锌构成的源极端子。栅极线直接连接到由氧化铟锌构成的栅极端子。或者，用于切换多个像素电极的薄膜晶体管的漏极直接连接到由氧化铟锌构成的像素电极。这些配置不需要对于传统的薄膜晶体管衬底是必需的钝化膜，并且所得到的薄膜晶体管衬底可以通过减少数量的制造步骤来制造。

5. 发明授权

US06432755B1 Thin film transistor and manufacturing method therefor 有权
公开(公告)号：US06432755B1
公开(公告)日：2002-08-13
申请号：US09938068
申请日：2001-08-22
申请人： Chae Gee Sung , Jo Gyoo Chul
发明人： Chae Gee Sung , Jo Gyoo Chul
IPC分类号： H01L2184
摘要： A TFT structure having sufficiently low resistance wiring is provided, in which characteristic defects thereof caused by undercuts in a barrier metal layer can be prevented, the undercuts formed in a step for processing a source and a drain electrode composed of copper. The TFT structure of the present invention comprises a gate electrode on a glass substrate, a gate insulation film, a semiconductor active layer disposed on the gate insulation film so as to oppose the gate electrode, ohmic contact layers formed on both edge portions of the semiconductor active layer, and a source and a drain electrode connected to the semiconductor active layer via the respective ohmic contact layers. In addition, the source electrode and the drain electrode are formed of copper, and barrier metal layers are formed on the bottom surfaces of the source electrode and the drain electrode above areas at which the upper surfaces of the respective ohmic contact layers are located.

6. 发明授权

US06350995B1 Thin film transistor and manufacturing method therefore 有权
标题翻译：因此薄膜晶体管及其制造方法
公开(公告)号：US06350995B1
公开(公告)日：2002-02-26
申请号：US09599772
申请日：2000-06-22
申请人： Chae Gee Sung , Jo Gyoo Chul
发明人： Chae Gee Sung , Jo Gyoo Chul
IPC分类号： H01L0100
CPC分类号： H01L27/12 , H01L27/124 , H01L29/458 , H01L29/66765
摘要： A TFT structure having sufficiently low resistance wiring is provided. The present invention prevents the characteristic defects caused by undercuts in a barrier metal layer. In the prior art, the undercuts are formed by a step for processing a source and a drain electrode composed of copper. The TFT structure of the present invention comprises a gate electrode on a glass substrate, a gate insulation film, a semiconductor active layer disposed on the gate insulation film so as to oppose the gate electrode, ohmic contact layers formed on both edge portions of the semiconductor active layer, and a source and a drain electrode connected to the semiconductor active layer via the respective ohmic contact layers. In addition, the source electrode and the drain electrode are formed of copper. Barrier metal layers are formed on the bottom surfaces of the source electrode and the drain electrode above areas at which the upper surfaces of the respective ohmic contact layers are located.
摘要翻译：提供具有足够低电阻布线的TFT结构。本发明防止了阻挡金属层中的底切引起的特征缺陷。在现有技术中，通过用于处理由铜组成的源电极和漏电极的步骤来形成底切。本发明的TFT结构包括在玻璃基板上的栅极电极，栅极绝缘膜，设置在栅极绝缘膜上以与栅电极相对的半导体有源层，形成在半导体的两个边缘部分上的欧姆接触层有源层以及经由各个欧姆接触层与半导体有源层连接的源极和漏极。此外，源电极和漏电极由铜形成。阻挡金属层形成在源电极和漏电极的底表面上方各欧姆接触层的上表面所在的区域上方。

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